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* board: ls2080ardb: qds: Fix compiling issue when FSL_MC_ENET not definedYork Sun2016-06-03-0/+8
| | | | | | | U-Boot should continue to work without management complex (MC). Fix compiling errors and warnings. Signed-off-by: York Sun <york.sun@nxp.com>
* board: ls102xa: Fix ICID setupVincent Siles2016-06-03-2/+5
| | | | | | | LS102A ref manual dictates that ICID have to be written to the MSB of the ICID register, not to the LSB. Signed-off-by: Vincent Siles <vincent.siles@provenrun.com>
* board/freescale: Update ddr clk_adjustShengzhou Liu2016-06-03-172/+172
| | | | | | | | | This patch updates clk_adjust to actual value for boards with T-series and LS-series SoCs to match the setting of clk_adjust in latest ddr driver. Signed-off-by: Shengzhou Liu <Shengzhou.Liu@nxp.com> Reviewed-by: York Sun <york.sun@nxp.com>
* Delete tests of CONFIG_OF_LIBFDT when testing CONFIG_OF_BOARD_SETUPRobert P. J. Day2016-05-27-2/+2
| | | | | | | | | | | | | | | | Since CONFIG_OF_BOARD_SETUP depends on CONFIG_OF_LIBFDT: config OF_BOARD_SETUP bool "Set up board-specific details in device tree before boot" depends on OF_LIBFDT ... remove superfluous tests of CONFIG_OF_LIBFDT when testing for CONFIG_OF_BOARD_SETUP. Signed-off-by: Robert P. J. Day <rpjday@crashcourse.ca> [trini: Typo fix: s/ifdefi/ifdef/] Signed-off-by: Tom Rini <trini@konsulko.com>
* Merge branch 'master' of git://git.denx.de/u-boot-mpc85xxTom Rini2016-05-25-2/+7
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| * powerpc:t4240rdb: Disable the non-existent ethernet ports on T4240RDBYing Zhang2016-05-24-0/+5
| | | | | | | | | | | | | | | | | | Disable the non-existent ethernet ports on T4240RDB:FM1_DTSEC5, FM1_DTSEC6, FM2_DTSEC5 and FM2_DTSEC6. Signed-off-by: Ying Zhang <ying.zhang22455@nxp.com> Acked-by: Joe Hershberger <joe.hershberger@ni.com> Reviewed-by: York Sun <york.sun@nxp.com>
| * powerpc/t208xrdb: Update MAINTAINERS fileYork Sun2016-05-19-1/+1
| | | | | | | | | | Signed-off-by: York Sun <york.sun@nxp.com> CC: Shengzhou Liu <Shengzhou.Liu@nxp.com>
| * powerpc/t208xqds: Update MAINTAINERS fileYork Sun2016-05-19-1/+1
| | | | | | | | | | Signed-off-by: York Sun <york.sun@nxp.com> CC: Shengzhou Liu <Shengzhou.Liu@nxp.com>
* | armv8: ls1043ardb: invert irq pin polarity for AQR105 PHYShaohui Xie2016-05-18-0/+4
| | | | | | | | | | | | | | | | | | To use AQR105 PHY's interrupt, we need to invert the IRQ pin polarity by setting relative bit in SCFG_INTPCR register, because AQR105 interrupt is low active but GIC accepts high active. Signed-off-by: Shaohui Xie <Shaohui.Xie@nxp.com> Reviewed-by: York Sun <york.sun@nxp.com>
* | arch/arm, arch/powerpc: add # of SEC engines on the SOCAlex Porosanu2016-05-18-1/+1
| | | | | | | | | | | | | | | | | | | | Some SOCs, specifically the ones in the C29x familiy can have multiple security engines. This patch adds a system configuration define which indicates the maximum number of SEC engines that can be found on a SoC. Signed-off-by: Alex Porosanu <alexandru.porosanu@nxp.com> Reviewed-by: York Sun <york.sun@nxp.com>
* | armv8: ls1043ardb: fix types of variablesQianyu Gong2016-05-18-3/+3
| | | | | | | | | | | | | | Using u16 for cfg_rcw_src and u8 for sd1refclk_sel is enough. Signed-off-by: Gong Qianyu <Qianyu.Gong@nxp.com> Reviewed-by: York Sun <york.sun@nxp.com>
* | armv8: ls1043a: remove redundant code in board filesQianyu Gong2016-05-18-9/+0
| | | | | | | | | | | | | | | | | | gd->env_addr will be initialized in env_init() in common/env_nowhere.c if CONFIG_ENV_IS_NOWHERE is defined. So no need to do it again. Signed-off-by: Gong Qianyu <Qianyu.Gong@nxp.com> Reviewed-by: York Sun <york.sun@nxp.com>
* | armv8/ls1043ardb: fix the limitation of using 'cpld reset'Qianyu Gong2016-05-18-2/+25
| | | | | | | | | | | | | | | | | | | | The current 'cpld reset' will just write global_rst register but couldn't switch to NOR boot if the board's switches are for NAND/SD boot. So need to write rcw source registers for NOR boot as well. Signed-off-by: Gong Qianyu <Qianyu.Gong@nxp.com> Reviewed-by: York Sun <york.sun@nxp.com>
* | arm: uniform usage of u32 in ls102x caam configVincent Siles2016-05-18-1/+1
| | | | | | | | | | | | | | Mix usage of uint32_t and u32 fixed in favor of u32. Signed-off-by: Vincent Siles <vincent.siles@provenrun.com> Reviewed-by: York Sun <york.sun@nxp.com>
* | arm: Fix SCFG ICID reg addressesVincent Siles2016-05-18-2/+2
| | | | | | | | | | | | | | | | | | | | | | | | | | On the LS102x boards, in order to initialize the ICID values of masters, the dev_stream_id array holds absolute offsets from the base of SCFG. In ls102xa_config_ssmu_stream_id, the base pointer is cast to uint32_t * before adding the offset, leading to an invalid address. Casting it to void * solves the issue. Signed-off-by: Vincent Siles <vincent.siles@provenrun.com> Reviewed-by: York Sun <york.sun@nxp.com>
* | armv8: ls2080a: Update MAINTAINERS filePrabhakar Kushwaha2016-05-17-2/+2
| | | | | | | | | | | | | | Update MAINTAINERS file for ls2080aqds and ls2080ardb platforms. Signed-off-by: Prabhakar Kushwaha <prabhakar.kushwaha@nxp.com> Reviewed-by: York Sun <york.sun@nxp.com>
* | armv8/ls2080ardb: Update DDR timing to support more UDIMMsShengzhou Liu2016-05-17-3/+3
| | | | | | | | | | | | | | | | | | | | | | | | | | | | Optimize DDR timing for good margins to support new Transcend and Apacer DDR4 UDIMM besides current Micron UDIMM. Verified 1333MT/s, 1600MT/s, 1866MT/s, 2133MT/s rate with following UDIMM on LS2080ARDB. - Micron UDIMM: MTA18ASF1G72AZ-2G1A1Z - Apacer UDIMM: 78.C1GM4.AF10B - Transcend UDIMM: TS1GLH72V1H Signed-off-by: Shengzhou Liu <Shengzhou.Liu@nxp.com> Reviewed-by: York Sun <york.sun@nxp.com>
* | armv8/ls1043: Add workaround for DDR erratum A-008850Shengzhou Liu2016-05-17-16/+8
|/ | | | | | | | | Barrier transactions from CCI400 need to be disabled till the DDR is configured, otherwise it may lead to system hang. The patch adds workaround to fix the erratum. Signed-off-by: Shengzhou Liu <Shengzhou.Liu@nxp.com> Reviewed-by: York Sun <york.sun@nxp.com>
* Fix various typos, scattered over the code.Robert P. J. Day2016-05-05-3/+3
| | | | | | | | | | | | | Spelling corrections for (among other things): * environment * override * variable * ftd (should be "fdt", for flattened device tree) * embedded * FTDI * emulation * controller
* Merge branch 'master' of git://www.denx.de/git/u-boot-imxTom Rini2016-04-13-29/+19
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| * mx6slevk: imximage.cfg: update to fix tINIT3 and tIH-CA violationsTom Rini2016-04-03-2/+2
| | | | | | | | | | | | | | | | | | | | | | | | | | | | Having had a similar board and memory part under logic analyzer, a tINIT3 violation was measured. The fix was involved keeping tXPR and SDE_to_RST at the power-on defaults and setting RST_to_CKE the JEDEC value for LPDDR2. There was also a tIH-CA violation and this was resolved by writing the default value in rather than what the script here uses. Cc: Fabio Estevam <fabio.estevam@nxp.com> Cc: Peng Fan <peng.fan@nxp.com> Signed-off-by: Tom Rini <trini@konsulko.com> Reviewed-by: Fabio Estevam <fabio.estevam@nxp.com>
| * mx6qarm2: imximage_mx6dl.cfg update to fix tINIT3 violationTom Rini2016-04-03-2/+2
| | | | | | | | | | | | | | | | | | | | | | Having had a similar board and memory part under logic analyzer, a tINIT3 violation was measured. The fix was involved keeping tXPR and SDE_to_RST at the power-on defaults and setting RST_to_CKE the JEDEC value for LPDDR2. Cc: Jason Liu <jason.hui.liu@nxp.com> Cc: Ye Li <ye.li@nxp.com> Signed-off-by: Tom Rini <trini@konsulko.com>
| * mx6sabresd: Remove unneeded enable_lvds() functionFabio Estevam2016-04-03-11/+1
| | | | | | | | | | | | | | | | | | | | enable_lvds() function only set bits IOMUXC_GPR2_DATA_WIDTH_CH0_18BIT and IOMUXC_GPR2_DATA_WIDTH_CH1_18BIT, but these bits were already set previously inside setup_display(). We can safely remove enable_lvds() then. Signed-off-by: Fabio Estevam <fabio.estevam@nxp.com>
| * mx6sabresd: Use VESA 1024x768 timingsFabio Estevam2016-03-25-14/+14
| | | | | | | | | | | | | | | | VESA 1024x768 results in much more accurate timings. Based on the patch from Soeren Moch for the tbs2910 board. Signed-off-by: Fabio Estevam <fabio.estevam@nxp.com>
* | armv8: LS2080A: Consolidate LS2080A and LS2085AYork Sun2016-04-06-47/+48
| | | | | | | | | | | | | | | | | | | | | | | | LS2080A is the primary SoC, and LS2085A is a personality with AIOP and DPAA DDR. The RDB and QDS boards support both personality. By detecting the SVR at runtime, a single image per board can support both SoCs. It gives users flexibility to swtich SoC without the need to reprogram the board. Signed-off-by: York Sun <york.sun@nxp.com> CC: Prabhakar Kushwaha <prabhakar.kushwaha@nxp.com> Reviewed-by: Prabhakar Kushwaha <prabhakar.kushwaha@nxp.com>
* | armv8: ls1043aqds: make sure fixed-link property is big endianShaohui Xie2016-04-06-6/+6
| | | | | | | | | | | | | | | | | | When setting fixed-link property to DTS, the values should be converted with using cpu_to_fdt32 so that to have correct value on little endian Soc. Signed-off-by: Shaohui Xie <Shaohui.Xie@nxp.com> Reviewed-by: York Sun <york.sun@nxp.com>
* | usb: Rename ehci-fsl.h to ehci-ci.hMateusz Kulikowski2016-04-01-6/+6
| | | | | | | | | | | | | | | | | | | | | | | | | | Most of ehci-fsl header describe USB controller designed by Chipidea and used by various SoC vendors. This patch renames it to a generic header: ehci-ci.h Contents of file are not changed (so it contains several references to freescale SoCs). Signed-off-by: Mateusz Kulikowski <mateusz.kulikowski@gmail.com> Acked-by: Marek Vasut <marex@denx.de> Tested-by: Simon Glass <sjg@chromium.org>
* | armv8/ls2080ardb: Enable VID supportRai Harninder2016-03-29-1/+23
| | | | | | | | | | | | | | | | This patch enable VID support for ls2080ardb platform. It uses the common VID driver. Signed-off-by: Rai Harninder <harninder.rai@nxp.com> Reviewed-by: York Sun <york.sun@nxp.com>
* | SECURE BOOT: Change fsl_secboot_validate func to pass image addrSaksham Jain2016-03-29-12/+26
| | | | | | | | | | | | | | | | | | Use a pointer to pass image address to fsl_secboot_validate(), instead of using environmental variable "img_addr". Signed-off-by: Aneesh Bansal <aneesh.bansal@nxp.com> Signed-off-by: Saksham Jain <saksham.jain@nxp.com> Reviewed-by: York Sun <york.sun@nxp.com>
* | SECURE BOOT: Halt execution when secure boot failSaksham Jain2016-03-29-1/+6
| | | | | | | | | | | | | | | | | | | | | | | | In case of fatal failure during secure boot execution (e.g. header not found), reset is asserted to stop execution. If the RESET_REQ is not tied to HRESET, this allows the execution to continue. Add esbh_halt() after the reset to make sure execution stops. Signed-off-by: Aneesh Bansal <aneesh.bansal@nxp.com> Signed-off-by: Saksham Jain <saksham.jain@nxp.com> Reviewed-by: York Sun <york.sun@nxp.com>
* | armv8: ls2080rdb: ls2080qds: Add secure boot supportSaksham Jain2016-03-29-2/+20
| | | | | | | | | | | | | | | | | | | | Sec_init has been called at the beginning to initialize SEC Block (CAAM) which is used by secure boot validation later for both ls2080a qds and rdb. 64-bit address in ESBC Header has been enabled. Secure boot defconfigs are created for boards (NOR boot). Signed-off-by: Saksham Jain <saksham.jain@nxp.com> Reviewed-by: York Sun <york.sun@nxp.com>
* | armv8: fsl-lsch3: Add new header for secure bootSaksham Jain2016-03-29-5/+30
| | | | | | | | | | | | | | | | | | | | | | | | | | | | For secure boot, a header is used to identify key table, signature and image address. A new header structure is added for lsch3. Currently key extension (IE) feature is not supported. Single key feature is not supported. Keys must be in table format. Hence, SRK (key table) must be present. Max key number has increase from 4 to 8. The 8th key is irrevocable. A new barker Code is used. Signed-off-by: Aneesh Bansal <aneesh.bansal@nxp.com> Signed-off-by: Saksham Jain <saksham.jain@nxp.com> Reviewed-by: York Sun <york.sun@nxp.com>
* | armv8: ls2080a: Update fdt path for fsl-mc nodeStuart Yoder2016-03-24-7/+7
| | | | | | | | | | | | | | | | | | | | | | | | The fsl-mc node has been moved under /soc, so update the path references accordingly. Backwards compatibility is retained for /fsl-mc. Delete backwards compatibility for the completely obsolete /fsl,dprc@0. Signed-off-by: Stuart Yoder <stuart.yoder@nxp.com> Reviewed-by: York Sun <york.sun@nxp.com>
* | armv8/ls1043aqds: Return i2c mux to default chennelWenbin Song2016-03-21-2/+4
| | | | | | | | | | | | | | Return i2c mux to the default channel after accessing retimer. Signed-off-by: Wenbin Song <wenbin.song@nxp.com> Reviewed-by: York Sun <york.sun@nxp.com>
* | freescale: vid: Return i2c mux to default channelWenbin Song2016-03-21-3/+9
| | | | | | | | | | | | | | | | IR chip is on one of the channels on multiplexed I2C-bus. Reset to default channel after accessing. Signed-off-by: Wenbin Song <wenbin.song@nxp.com> Reviewed-by: York Sun <york.sun@nxp.com>
* | armv8: ls2085a: Remove phy configuration from QDS and RDBPrabhakar Kushwaha2016-03-21-64/+0
| | | | | | | | | | | | | | | | | | As phy_connect and phy_config are being called from DPAA2 driver. Remove calling of mentioned function from board file. Signed-off-by: Pratiyush Mohan Srivastava <pratiyush.srivastava@nxp.com> Signed-off-by: Prabhakar Kushwaha <prabhakar.kushwaha@nxp.com> Reviewed-by: York Sun <york.sun@nxp.com>
* | armv8: ls2080ardb: invert irq pins polarity for AQR405 PHYShaohui Xie2016-03-21-0/+4
|/ | | | | | | | | To use AQR405 PHY's interrupt, we need to invert the relative IRQ pins polarity by setting IRQCR register, because AQR405 interrupt is low active but GIC accepts high active. Signed-off-by: Shaohui Xie <Shaohui.Xie@nxp.com> Reviewed-by: York Sun <york.sun@nxp.com>
* Kconfig: Move CONFIG_FIT and related options to KconfigSimon Glass2016-03-14-0/+3
| | | | | | | | | | | | | | | | | | | | | | | | | | | | | There are already two FIT options in Kconfig but the CONFIG options are still in the header files. We need to do a proper move to fix this. Move these options to Kconfig and tidy up board configuration: CONFIG_FIT CONFIG_OF_BOARD_SETUP CONFIG_OF_SYSTEM_SETUP CONFIG_FIT_SIGNATURE CONFIG_FIT_BEST_MATCH CONFIG_FIT_VERBOSE CONFIG_OF_STDOUT_VIA_ALIAS CONFIG_RSA Unfortunately the first one is a little complicated. We need to make sure this option is not enabled in SPL by this change. Also this option is enabled automatically in the host builds by defining CONFIG_FIT in the image.h file. To solve this, add a new IMAGE_USE_FIT #define which can be used in files that are built on the host but must also build for U-Boot and SPL. Note: Masahiro's moveconfig.py script is amazing. Signed-off-by: Simon Glass <sjg@chromium.org> [trini: Add microblaze change, various configs/ re-applies] Signed-off-by: Tom Rini <trini@konsulko.com>
* mx6slevk: Fix the power up of the Ethernet PHYFabio Estevam2016-03-13-5/+4
| | | | | | | | | GPIO4_21 is the LAN8720 power pin, not the LAN8720 reset pin. Fix that, so that we can have Ethernet functional again. Reviewed-by: Tom Rini <trini@konsulko.com> Signed-off-by: Fabio Estevam <fabio.estevam@nxp.com>
* mx6qarm2: Update maintainer's emailsFabio Estevam2016-03-02-2/+2
| | | | | | Use the new NXP emails. Signed-off-by: Fabio Estevam <fabio.estevam@nxp.com>
* MAINTAINERS: Update Peng Fan's email addressFabio Estevam2016-03-02-3/+3
| | | | | | | Use Peng Fan's new NXP email address in MAINTAINERS files. Signed-off-by: Fabio Estevam <fabio.estevam@nxp.com> Acked-by: Peng Fan <peng.fan@nxp.com>
* armv7: ls102xa: Move smmu and stream id initialization into the common soc codeAlison Wang2016-02-24-83/+2
| | | | | | | | The initialization for smmu and stream id is moved into the common soc code. Signed-off-by: Alison Wang <alison.wang@nxp.com> Reviewed-by: York Sun <york.sun@nxp.com>
* board: ls1043ardb: Modify pin-muxing code for USB and QE-HDLCZhao Qiang2016-02-24-10/+43
| | | | | | | | | QE-HDLC and USB multi-use the pins, modify the pin-muxing code for them, when set "hwconfig=qe-hdlc" in uboot, assign the pins to QE-HDLC, if not, assgin it to USB Signed-off-by: Zhao Qiang <qiang.zhao@nxp.com> Reviewed-by: York Sun <york.sun@nxp.com>
* board: ls1043rdb: Move USB muxing config to config_board_muxZhao Qiang2016-02-24-15/+15
| | | | | | | | Pin-muxing code should be in config_board_mux, move USB muxing config to config_board_mux. Signed-off-by: Zhao Qiang <qiang.zhao@nxp.com> Reviewed-by: York Sun <york.sun@nxp.com>
* board: ls1043ardb: Add micro QE support for ls1043ardbZhao Qiang2016-02-24-0/+8
| | | | | Signed-off-by: Zhao Qiang <qiang.zhao@nxp.com> Reviewed-by: York Sun <york.sun@nxp.com>
* armv8/ls1043aqds: Add USB support for ls1043aqdsQianyu Gong2016-02-24-0/+15
| | | | | | | Add USB XHCI support for ls1043qds board. Signed-off-by: Gong Qianyu <Qianyu.Gong@nxp.com> Reviewed-by: York Sun <york.sun@nxp.com>
* qe: move drivers/qe/qe.h to include/fsl_qe.hQianyu Gong2016-02-24-4/+4
| | | | | | | | As the QE firmware struct is shared with Fman, move the header file out of drivers/qe/. Signed-off-by: Gong Qianyu <Qianyu.Gong@nxp.com> Reviewed-by: York Sun <york.sun@nxp.com>
* arm: ls1021a: Add QSPI or IFC support in SD boot for LS1021AQDS boardAlison Wang2016-02-24-3/+18
| | | | | | | | | | | | | | As QSPI and IFC are pin-multiplexed on LS1021A, only IFC is supported in SD boot now. For the customer's demand, QSPI needs to be supported in SD boot too. This patch adds QSPI or IFC support in SD boot according to the corresponding defconfig. For detail, ls1021aqds_sdcard_ifc_defconfig is used to support IFC in SD boot and ls1021aqds_sdcard_qspi_defconfig is used to support QSPI in SD boot. Signed-off-by: Alison Wang <alison.wang@nxp.com> Reviewed-by: York Sun <york.sun@nxp.com>
* Merge branch 'master' of git://www.denx.de/git/u-boot-imxTom Rini2016-02-21-24/+19
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| * mx7dsabresd: Make 'ums' command functionalFabio Estevam2016-02-21-23/+18
| | | | | | | | | | | | | | | | | | | | | | | | | | | | When running the 'ums' command we get: => ums 0 mmc 0 UMS: disk start sector: 0x0, count: 0xe18000 g_dnl_register: failed!, error: -22 ERROR: g_dnl_register failed at common/cmd_usb_mass_storage.c:107/do_usb_mass_storage() Fix this by initializing USB OTG1 port as USB device mode instead of host. Signed-off-by: Fabio Estevam <fabio.estevam@nxp.com>
generated by cgit v1.1 at 2024-11-01 20:33:13 +0000