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authorShengzhou Liu <Shengzhou.Liu@nxp.com>2016-04-07 14:41:30 +0800
committerYork Sun <york.sun@nxp.com>2016-05-17 09:26:59 -0700
commitaa7a2226b5a7829915d189d727ee9320dc3a198b (patch)
tree8df0a56bc5c981aa458339daf53571ca86adbd29 /board/freescale
parent5fc62fe57097e195a8047859cd3c278a5d6790b6 (diff)
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armv8/ls2080ardb: Update DDR timing to support more UDIMMs
Optimize DDR timing for good margins to support new Transcend and Apacer DDR4 UDIMM besides current Micron UDIMM. Verified 1333MT/s, 1600MT/s, 1866MT/s, 2133MT/s rate with following UDIMM on LS2080ARDB. - Micron UDIMM: MTA18ASF1G72AZ-2G1A1Z - Apacer UDIMM: 78.C1GM4.AF10B - Transcend UDIMM: TS1GLH72V1H Signed-off-by: Shengzhou Liu <Shengzhou.Liu@nxp.com> Reviewed-by: York Sun <york.sun@nxp.com>
Diffstat (limited to 'board/freescale')
-rw-r--r--board/freescale/ls2080ardb/ddr.h6
1 files changed, 3 insertions, 3 deletions
diff --git a/board/freescale/ls2080ardb/ddr.h b/board/freescale/ls2080ardb/ddr.h
index bda9d4a..b3c6306 100644
--- a/board/freescale/ls2080ardb/ddr.h
+++ b/board/freescale/ls2080ardb/ddr.h
@@ -29,9 +29,9 @@ static const struct board_specific_parameters udimm0[] = {
* ranks| mhz| GB |adjst| start | ctl2 | ctl3
*/
{2, 1350, 0, 4, 6, 0x0708090B, 0x0C0D0E09,},
- {2, 1666, 0, 4, 8, 0x08090B0D, 0x0E10100C,},
- {2, 1900, 0, 4, 8, 0x090A0C0E, 0x1012120D,},
- {2, 2300, 0, 4, 9, 0x0A0B0C10, 0x1114140E,},
+ {2, 1666, 0, 5, 9, 0x090A0B0E, 0x0F11110C,},
+ {2, 1900, 0, 6, 0xA, 0x0B0C0E11, 0x1214140F,},
+ {2, 2300, 0, 6, 0xB, 0x0C0D0F12, 0x14161610,},
{}
};