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authorQianyu Gong <qianyu.gong@nxp.com>2016-04-25 16:38:35 +0800
committerYork Sun <york.sun@nxp.com>2016-05-18 08:51:44 -0700
commit869bf86811a7c942dc48b294d5c0442b1f57ab53 (patch)
treebc8b01eeab4b8d0260e9559efb3775c8a4b3e60e /board/freescale
parent12cbf20d78f93c86e287d86ff863926e5cde9355 (diff)
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armv8/ls1043ardb: fix the limitation of using 'cpld reset'
The current 'cpld reset' will just write global_rst register but couldn't switch to NOR boot if the board's switches are for NAND/SD boot. So need to write rcw source registers for NOR boot as well. Signed-off-by: Gong Qianyu <Qianyu.Gong@nxp.com> Reviewed-by: York Sun <york.sun@nxp.com>
Diffstat (limited to 'board/freescale')
-rw-r--r--board/freescale/ls1043ardb/cpld.c26
-rw-r--r--board/freescale/ls1043ardb/cpld.h1
2 files changed, 25 insertions, 2 deletions
diff --git a/board/freescale/ls1043ardb/cpld.c b/board/freescale/ls1043ardb/cpld.c
index 78c2824..c645283 100644
--- a/board/freescale/ls1043ardb/cpld.c
+++ b/board/freescale/ls1043ardb/cpld.c
@@ -28,10 +28,18 @@ void cpld_write(unsigned int reg, u8 value)
/* Set the boot bank to the alternate bank */
void cpld_set_altbank(void)
{
+ u16 reg = CPLD_CFG_RCW_SRC_NOR;
u8 reg4 = CPLD_READ(soft_mux_on);
+ u8 reg5 = (u8)(reg >> 1);
+ u8 reg6 = (u8)(reg & 1);
u8 reg7 = CPLD_READ(vbank);
- CPLD_WRITE(soft_mux_on, reg4 | CPLD_SW_MUX_BANK_SEL);
+ cpld_rev_bit(&reg5);
+
+ CPLD_WRITE(soft_mux_on, reg4 | CPLD_SW_MUX_BANK_SEL | 1);
+
+ CPLD_WRITE(cfg_rcw_src1, reg5);
+ CPLD_WRITE(cfg_rcw_src2, reg6);
reg7 = (reg7 & ~CPLD_BANK_SEL_MASK) | CPLD_BANK_SEL_ALTBANK;
CPLD_WRITE(vbank, reg7);
@@ -42,7 +50,21 @@ void cpld_set_altbank(void)
/* Set the boot bank to the default bank */
void cpld_set_defbank(void)
{
- CPLD_WRITE(global_rst, 1);
+ u16 reg = CPLD_CFG_RCW_SRC_NOR;
+ u8 reg4 = CPLD_READ(soft_mux_on);
+ u8 reg5 = (u8)(reg >> 1);
+ u8 reg6 = (u8)(reg & 1);
+
+ cpld_rev_bit(&reg5);
+
+ CPLD_WRITE(soft_mux_on, reg4 | CPLD_SW_MUX_BANK_SEL | 1);
+
+ CPLD_WRITE(cfg_rcw_src1, reg5);
+ CPLD_WRITE(cfg_rcw_src2, reg6);
+
+ CPLD_WRITE(vbank, 0);
+
+ CPLD_WRITE(system_rst, 1);
}
void cpld_set_nand(void)
diff --git a/board/freescale/ls1043ardb/cpld.h b/board/freescale/ls1043ardb/cpld.h
index bd59c0e..cb175b5 100644
--- a/board/freescale/ls1043ardb/cpld.h
+++ b/board/freescale/ls1043ardb/cpld.h
@@ -40,6 +40,7 @@ void cpld_rev_bit(unsigned char *value);
#define CPLD_SW_MUX_BANK_SEL 0x40
#define CPLD_BANK_SEL_MASK 0x07
#define CPLD_BANK_SEL_ALTBANK 0x04
+#define CPLD_CFG_RCW_SRC_NOR 0x025
#define CPLD_CFG_RCW_SRC_NAND 0x106
#define CPLD_CFG_RCW_SRC_SD 0x040
#endif