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* Merge branch 'master' of git://git.denx.de/u-boot-usbTom Rini2016-06-18-0/+8
|\ | | | | | | | | | | | | Signed-off-by: Tom Rini <trini@konsulko.com> Conflicts: arch/arm/include/asm/arch-fsl-layerscape/immap_lsch3.h
| * usb: xhci: fsl: Add workaround for USB erratum A008751Sriram Dash2016-06-13-0/+1
| | | | | | | | | | | | | | | | | | This patch is doing the following: 1. Implementing the errata for LS2080. 2. Adding fixup for fdt for LS2080. Signed-off-by: Sriram Dash <sriram.dash@nxp.com> Signed-off-by: Rajesh Bhagat <rajesh.bhagat@nxp.com>
| * arm64: fsl-layerscape: add get_svr and IS_SVR_REV helperSriram Dash2016-06-13-0/+7
| | | | | | | | | | | | | | | | Adds get_svr and IS_SVR_REV helpers for ARMv8 platforms, similar to PPC and ARMv7. Signed-off-by: Sriram Dash <sriram.dash@nxp.com> Signed-off-by: Rajesh Bhagat <rajesh.bhagat@nxp.com>
* | arm: Fix setjmpAlexander Graf2016-06-17-5/+4
| | | | | | | | | | | | | | | | | | | | The setjmp/longjmp implementation did not work on thumb1 implementations because it used instruction encodings that don't exist on thumb1 yet. This patch limits itself to thumb1 instruction set for 32bit arm and removes a superfluous printf along the way. Signed-off-by: Alexander Graf <agraf@suse.de>
* | armv8: s32v234: Introduce basic support for s32v234evbEddy Petrișor2016-06-13-0/+1318
| | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | Add initial support for NXP's S32V234 SoC and S32V234EVB board. The S32V230 family is designed to support computation-intensive applications for image processing. The S32V234, as part of the S32V230 family, is a high-performance automotive processor designed to support safe computation-intensive applications in the area of vision and sensor fusion. Code originally writen by: Original-signed-off-by: Stoica Cosmin-Stefan <cosminstefan.stoica@freescale.com> Original-signed-off-by: Mihaela Martinas <Mihaela.Martinas@freescale.com> Original-signed-off-by: Eddy Petrișor <eddy.petrisor@gmail.com> Signed-off-by: Eddy Petrișor <eddy.petrisor@nxp.com>
* | board: arm:: Add support for Broadcom BCM23550Steve Rae2016-06-13-0/+46
| | | | | | | | | | | | Add support for the Broadcom BCM23550 board. Signed-off-by: Steve Rae <srae@broadcom.com>
* | Merge branch 'master' of http://git.denx.de/u-boot-sunxiTom Rini2016-06-12-0/+5
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| * | sunxi: Downclock AHB1 to 100MHz on Allwinner A64Siarhei Siamashka2016-06-10-0/+5
| |/ | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | Currently the AHB1 clock speed is configured as 200MHz by the SPL, but this causes a subtle and hard to reproduce data corruption in SRAM C (for example, this can't be easily detected with a trivial memset/memcmp test). For what it's worth, the Allwinner's BSP configures AHB1 as 200MHz, as can be verified by running the devmem2 tool in the system running the Allwinner's kernel 3.10.x: 0x1C20028: PLL_PERIPH0_CTRL_REG = 0x90041811 0x1C20054: AHB1_APB1_CFG_REG = 0x3180 0x1C20058: APB2_CFG_REG = 0x1000000 0x1C2005C: AHB2_CFG_REG = 0x1 However the FEL mode uses more conservative settings (100MHz for AHB1): 0x1C20028: PLL_PERIPH0_CTRL_REG = 0x90041811 0x1C20054: AHB1_APB1_CFG_REG = 0x3190 0x1C20058: APB2_CFG_REG = 0x1000000 0x1C2005C: AHB2_CFG_REG = 0x0 It is yet to be confirmed whether faster AHB1/AHB2 clock settings can be used safely if we initialize the AXP803 PMIC instead of using reset defaults. But in order to resolve the data corruption problem right now, it's best to downclock AHB1 to a safe level. Note that this issue only affects the SPL, which is not fully supported on Allwinner A64 yet and it should not affect the boot0 usage (unless somebody can confirm SRAM C corruption with the boot0 too). Signed-off-by: Siarhei Siamashka <siarhei.siamashka@gmail.com> Acked-by: Hans de Goede <hdegoede@redhat.com> Signed-off-by: Hans de Goede <hdegoede@redhat.com>
* | Merge branch 'master' of git://www.denx.de/git/u-boot-imxTom Rini2016-06-12-0/+8
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| * | imx-common: introduce simpler macros for runtime dectionPeng Fan2016-05-24-0/+8
| | | | | | | | | | | | | | | | | | | | | | | | Introduce simpler macros for runtime cpu dection. Signed-off-by: Peng Fan <van.freenix@gmail.com> Cc: Stefano Babic <sbabic@denx.de> Acked-by: Stefano Babic <sbabic@denx.de>
* | | armv8: ls2080aqds: Enable QSPI boot supportYuan Yao2016-06-10-0/+4
| | | | | | | | | | | | | | | | | | | | | | | | | | | This patch adds QSPI boot support for LS2080AQDS board. The QSPI boot image need to be programmed into the QSPI flash first. Then we can switch to booting from QSPI memory space. Signed-off-by: Yuan Yao <yao.yuan@nxp.com> Reviewed-by: York Sun <york.sun@nxp.com>
* | | armv8: ls2080aqds: Config QSPI pin mux via FPGA in NAND bootYuan Yao2016-06-10-0/+2
| | | | | | | | | | | | | | | Signed-off-by: Yuan Yao <yao.yuan@nxp.com> Reviewed-by: York Sun <york.sun@nxp.com>
* | | armv8: ls2080aqds: Select QSPI CLK div via SCFGYuan Yao2016-06-10-0/+1
| | | | | | | | | | | | | | | | | | | | | QSPI module output SCLK divisor value is configured through SCFG. Signed-off-by: Yuan Yao <yao.yuan@nxp.com> Reviewed-by: York Sun <york.sun@nxp.com>
* | | armv8/ls2080a: configure PMU's PCTBENR to enable WDTYunhui Cui2016-06-10-0/+1
| |/ |/| | | | | | | | | | | | | | | The SP805-WDT module on LS2080A requires configuration of PMU's PCTBENR register to enable watchdog counter decrement and reset signal generation. The watchdog clock needs to be enabled first. Signed-off-by: Yunhui Cui <yunhui.cui@nxp.com> Reviewed-by: York Sun <york.sun@nxp.com>
* | arm, am335x: Enable Spread Spectrum for the MPUHeiko Schocher2016-06-09-1/+3
| | | | | | | | | | | | | | | | Enable Spread Spectrum for the MPU by calculating the required values and setting the registers accordingly. Signed-off-by: Heiko Schocher <hs@denx.de> Reviewed-by: Tom Rini <trini@konsulko.com>
* | am335x: add some missing CM_CLKMODE_DPLL_SSC macrosHeiko Schocher2016-06-09-0/+3
| | | | | | | | | | | | | | | | | | | | add missing CM_CLKMODE_DPLL_SSC_ACK_MASK, CM_CLKMODE_DPLL_SSC_DOWNSPREAD_MASK and CM_CLKMODE_DPLL_SSC_TYPE_MASK defines. Used for enabling spread spectrum. Signed-off-by: Heiko Schocher <hs@denx.de> Reviewed-by: Tom Rini <trini@konsulko.com>
* | arm, am335x: add some missing GPIO register definitionsHeiko Schocher2016-06-09-0/+2
| | | | | | | | | | | | | | | | | | add missing: OMAP_GPIO_IRQSTATUS_SET_0 and OMAP_GPIO_IRQSTATUS_SET_1 registers. Signed-off-by: Heiko Schocher <hs@denx.de> Reviewed-by: Tom Rini <trini@konsulko.com>
* | arm/arm64: implement a boot header capabilityAndre Przywara2016-06-06-0/+29
| | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | Some SPL loaders (like Allwinner's boot0, and Broadcom's boot0) require a header before the actual U-Boot binary to both check its validity and to find other data to load. Sometimes this header may only be a few bytes of information, and sometimes this might simply be space that needs to be reserved for a post-processing tool. Introduce a config option to allow assembler preprocessor commands to be inserted into the code at the appropriate location; typical assembler preprocessor commands might be: .space 1000 .word 0x12345678 Signed-off-by: Andre Przywara <andre.przywara@arm.com> Signed-off-by: Steve Rae <srae@broadcom.com> Commit Notes: Please note that the current code: start.S (arm64) and vectors.S (arm) already jumps over some portion of data already, so this option basically just increases the size of this region (and the resulting binary). For use with Allwinner's boot0 blob there is a tool called boot0img[1], which fills the header to allow booting A64 based boards. For the Pine64 we need a 1536 byte header (including the branch instruction) at the moment, so we add this to the defconfig. [1] https://github.com/apritzel/pine64/tree/master/tools END Reviewed-by: Tom Rini <trini@konsulko.com>
* | arm: Introduce setjmp/longjmpAlexander Graf2016-06-06-0/+99
| | | | | | | | | | | | | | | | | | | | | | To quit an EFI application we will need logic to jump to the caller of a function without returning from the function we called into, so we need setjmp/longjmp functionality. This patch introduces a trivial implementation of these that I verified works on armv7, thumb2 and aarch64. Signed-off-by: Alexander Graf <agraf@suse.de>
* | Fix to davinci_nand.h to place CEnCFG registers at correctPeter Howard2016-06-06-4/+6
| | | | | | | | Signed-off-by: Peter Howard <phoward@gme.net.au>
* | Merge branch 'master' of git://git.denx.de/u-boot-fsl-qoriqTom Rini2016-06-04-1/+47
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| * | armv8: fsl-layerscape: Add support of QorIQ LS1012A SoCPrabhakar Kushwaha2016-06-03-0/+46
| | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | The QorIQ LS1012A processor, optimized for battery-backed or USB-powered, integrates a single ARM Cortex-A53 core with a hardware packet forwarding engine and high-speed interfaces to deliver line-rate networking performance. This patch add support of LS1012A SoC along with - Update platform & DDR clock read logic as per SVR - Define MMDC controller register set. - Update LUT base address for PCIe - Avoid L3 platform cache compilation - Update USB address, errata - SerDes table - Added CSU IDs for SDHC2, SAI-1 to SAI-4 Signed-off-by: Calvin Johnson <calvin.johnson@nxp.com> Signed-off-by: Makarand Pawagi <makarand.pawagi@mindspeed.com> Signed-off-by: Prabhakar Kushwaha <prabhakar.kushwaha@nxp.com> Reviewed-by: York Sun <york.sun@nxp.com>
| * | armv8: fsl-layerscape: Avoid LS1043A specifc definesPrabhakar Kushwaha2016-06-03-1/+1
| | | | | | | | | | | | | | | | | | | | | | | | Other than LS1043A, LS1012A also Chassis Gen2 Architecture compliant. So Avoid LS1043A specific defines in arch/arm Signed-off-by: Prabhakar Kushwaha <prabhakar.kushwaha@nxp.com> Reviewed-by: York Sun <york.sun@nxp.com>
* | | Merge branch 'master' of git://git.denx.de/u-boot-tegraTom Rini2016-06-03-996/+30
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| * | | ARM: tegra: add core Tegra186 supportStephen Warren2016-05-31-0/+26
| | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | This adds the bare minimum code to support Tegra186, with UART and eMMC working. The empty gpio.h is required because <asm/gpio.h> includes it. A future cleanup round may be able to solve this for all Tegra generations at once. mach-tegra/Makefile is adjusted not to compile anything for Tegra186, but instead to defer everything to mach-tegra/tegra186/Makefile. This allows the SoC code to pick-and-choose which of the C files in the "common" mach-tegra/ directory to compile in based on the SoC's needs. Most of the code is not valid for Tegra186, and this approach removes the need for mach-tegra/Makefile to contain many SoC-specific ifdefs. This approach may be applied to all other Tegra SoCs in a future cleanup round. board186.c is introduced to replace board.c and board2.c. These files currently contain a slew of SoC- and board-specific code that is not valid for Tegra186. This approach avoids adding yet more ifdefs to those files. A future cleanup round may refactor most of board*.c into board-/ SoC-specific functions files thus allowing the top-level functions like board_init_early_f to be shared again. Signed-off-by: Stephen Warren <swarren@nvidia.com> Reviewed-by: Simon Glass <sjg@chromium.org> Signed-off-by: Tom Warren <twarren@nvidia.com>
| * | | mmc: tegra: add basic Tegra186 supportStephen Warren2016-05-31-0/+2
| | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | Tegra186's MMC controller needs to be explicitly identified. Add another compatible value for it. Tegra186 will use an entirely different clock/reset control mechanism to existing chips, and will use standard clock/reset APIs rather than the existing Tegra-specific custom APIs. The driver support for that isn't ready yet, so simply disable all clock/reset usage if compiling for Tegra186. This must happen at compile time rather than run-time since the custom APIs won't even be compiled in on Tegra186. In the long term, the plan would be to convert the existing custom APIs to standard APIs and get rid of the ifdefs completely. The system's main eMMC will work without any clock/reset support, since the firmware will have already initialized the controller in order to load U-Boot. Hence the driver is useful even in this apparently crippled state. Signed-off-by: Stephen Warren <swarren@nvidia.com> Signed-off-by: Tom Warren <twarren@nvidia.com>
| * | | ARM: tegra: use DT bindings for GPIO namingStephen Warren2016-05-31-996/+2
| |/ / | | | | | | | | | | | | | | | | | | | | | | | | | | | There are currently many places that define the list of all Tegra GPIOs; the DT binding header and custom Tegra-specific header file gpio.h. Fix the redundancy by replacing everything with the DT binding header file. Signed-off-by: Stephen Warren <swarren@nvidia.com> Reviewed-by: Simon Glass <sjg@chromium.org> Signed-off-by: Tom Warren <twarren@nvidia.com>
* | | arm: omap: Introduce vcores_init functionKeerthy2016-06-02-0/+1
| | | | | | | | | | | | | | | | | | | | | | | | The pmic registers for variants of am57xx boards are different hence we need to assign them carefully based on the board type. Add a function to assign omap_vcores after the board detection. Signed-off-by: Keerthy <j-keerthy@ti.com>
* | | ARM: DRA7: Add macros for voltage values for all OPPsAnna, Suman2016-06-02-6/+23
| | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | Define specific macros for the voltage values for all voltage domains for all applicable OPPs - OPP_NOM, OPP_OD and OPP_HIGH. No separate macros are defined for VD_MPU and VD_CORE at OPP_OD and OPP_HIGH as these use the same values as OPP_NOM. The current macros will be used as common macros that can be redefined appropriately based on a selected OPP configuration at build time. Signed-off-by: Suman Anna <s-anna@ti.com> Reviewed-by: Lokesh Vutla <lokeshvutla@ti.com>
* | | ARM: DRA7: Consolidate voltage macros across different SoCsAnna, Suman2016-06-02-13/+6
| | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | The voltage values for each voltage domain at an OPP is identical across all the SoCs in the DRA7 family. The current code defines one set of macros for DRA75x/DRA74x SoCs and another set for DRA72x macros. Consolidate both these sets into a single set. This is done so as to minimize the number of macros used when voltage values will be added for other OPPs as well. Signed-off-by: Suman Anna <s-anna@ti.com> Reviewed-by: Lokesh Vutla <lokeshvutla@ti.com>
* | | ARM: DRA7: Define common macros for efuse register offsetsAnna, Suman2016-06-02-0/+7
| | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | Define a set of common macros for the efuse register offsets (different for each OPP) that are used to get the AVS Class 0 voltage values and ABB configuration values. Assign these common macros to the register offsets for OPP_NOM by default for all voltage domains. These common macros can then be redefined properly to point to the OPP specific efuse register offset based on the desired OPP to program a specific voltage domain. Signed-off-by: Suman Anna <s-anna@ti.com> Reviewed-by: Lokesh Vutla <lokeshvutla@ti.com>
* | | ARM: DRA7: Update/Correct MPU and CORE OPP_NOM voltage valuesAnna, Suman2016-06-02-4/+4
| | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | The current OPP_NOM voltage values defined for the MPU and CORE voltage domains are based on the initial DRA75x_74x_SR1.1_DM data manual. As per this DM, the PMIC boot voltage can be set to either 1.10V or 1.15V for VD_MPU, and either 1.06V or 1.15V for VD_CORE. While the current values are correct, the latter set of values are the values that are common across all DRA75x, DRA72x SoCs and for all current Silicon revisions. So, update both the MPU and CORE OPP_NOM voltages to 1.15V. The macros are also slightly reorganized so that both the MPU and CORE voltage domain values are defined together. Signed-off-by: Suman Anna <s-anna@ti.com> Reviewed-by: Lokesh Vutla <lokeshvutla@ti.com>
* | | dra7xx: Enable USB_PHY3 32KHz clockRoger Quadros2016-06-02-0/+1
| | | | | | | | | | | | | | | | | | | | | DRA7xx has a 32KHz PHY clock for USB_PHY3 that must be enabled for USB1 instance in Super-Speed. Signed-off-by: Roger Quadros <rogerq@ti.com>
* | | arm: include: Import unified.h from Linux kernelMarek Vasut2016-06-02-0/+130
|/ / | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | Import unified.h from Linux kernel 4.4.6 , commit 0d1912303e54ed1b2a371be0bba51c384dd57326 . This header file contains macros used in libgcc functions in Linux kernel on ARM and will be needed for the libgcc sync. Since unified.h defines the W(instr) macro, we must drop this from the macro from memcpy.S , otherwise this triggers a warning about symbol redefinition. In order to keep the changes to unified.h to the minimum, tweak arch/arm/lib/Makefile such that it defines the CONFIG_ARM_ASM_UNIFIED macro, which places .syntax unified into all of the assembler files. This is mandatory. Moreover, for Thumb2 build, define CONFIG_THUMB2_KERNEL macro if and only if Thumb2 build is enabled. This macro is checked by unified.h and toggles between ARM and Thumb2 variant of the instructions in the assembler source files. Finally, this patch defines __LINUX_ARM_ARCH__=N macro based on the new CONFIG_SYS_ARM_ARCH Kconfig option. This macro selects between more optimal and more dense codepaths which work on armv5 and newer and less optimal codepaths which work on armv4 and possible armv3m. Tegra2 needs the same special handling as it does in arch/arm/Makefile to cater for the arm720t boot core. Signed-off-by: Marek Vasut <marex@denx.de> Cc: Albert Aribaud <albert.u.boot@aribaud.net> Cc: Masahiro Yamada <yamada.masahiro@socionext.com> Cc: Simon Glass <sjg@chromium.org> Cc: Tom Rini <trini@konsulko.com> Reviewed-by: Tom Rini <trini@konsulko.com>
* | Merge git://git.denx.de/u-boot-rockchipTom Rini2016-05-27-0/+70
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| * | rockchip: rk3288: grf: Define GRF_SOC_CON1 and GRF_SOC_CON3Sjoerd Simons2016-05-27-0/+53
| | | | | | | | | | | | | | | | | | | | | | | | Add definitions for GRF_SOC_CON1 and GRF_SOC_CON3 which contain various GMAC related fields. Signed-off-by: Sjoerd Simons <sjoerd.simons@collabora.co.uk> Reviewed-by: Simon Glass <sjg@chromium.org>
| * | rockchip: rk3288: Add clock support for the gmac ethernet interfaceSjoerd Simons2016-05-27-0/+17
| | | | | | | | | | | | | | | | | | | | | | | | | | | Setup the clocks for the gmac ethernet interface. This assumes the mac clock is fed by an external clock which is common on RK3288 based devices. Signed-off-by: Sjoerd Simons <sjoerd.simons@collabora.co.uk> Reviewed-by: Simon Glass <sjg@chromium.org>
* | | ARM: AM33xx: Add support for Clock SynthesizerLokesh Vutla2016-05-27-0/+43
| | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | The CDCE913 and CDCEL913 devices are modular PLL-based, low cost, high performance , programmable clock synthesizers. They generate upto 3 output clocks from a single input frequency. Each output can be programmed for any clock-frequency. Adding support for the same. Reviewed-by: Tom Rini <trini@konsulko.com> Signed-off-by: Lokesh Vutla <lokeshvutla@ti.com>
* | | board: AM335x-ICEv2: Add DDR dataLokesh Vutla2016-05-27-0/+15
| | | | | | | | | | | | | | | | | | | | | | | | | | | AM335x ICEv2 contains a 2Gbit(128Mx16) of DDR3 SDRAM(MT41J128M16JT-125), capable of running at 400MHz. Adding this specific DDR configuration details running at 400MHz. Reviewed-by: Tom Rini <trini@konsulko.com> Signed-off-by: Lokesh Vutla <lokeshvutla@ti.com>
* | | ARM: omap-common: Add device type to CPU stringDaniel Allred2016-05-27-6/+12
| | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | Update the CPU string output so that the device type is now included as part of the CPU string that is printed as the SPL or u-boot comes up. This update adds a suffix of the form "-GP" or "-HS" for production devices, so that general purpose (GP) and high security (HS) can be distiguished. Applies to all OMAP5 variants. Signed-off-by: Daniel Allred <d-allred@ti.com> Signed-off-by: Madan Srinivas <madans@ti.com> Reviewed-by: Tom Rini <trini@konsulko.com>
* | | arm: meson: implement calls to secure monitorBeniamino Galvani2016-05-27-0/+12
| | | | | | | | | | | | | | | | | | Implement calls to secure monitor to read the MAC address from e-fuse. Signed-off-by: Beniamino Galvani <b.galvani@gmail.com>
* | | arm: add initial support for Amlogic Meson and ODROID-C2Beniamino Galvani2016-05-27-0/+52
| | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | This adds platform code for the Amlogic Meson GXBaby (S905) SoC and a board definition for ODROID-C2. This initial submission only supports UART and Ethernet (through the existing Designware driver). DTS files are the ones submitted to Linux arm-soc for 4.7 [1]. [1] https://patchwork.ozlabs.org/patch/603583/ Signed-off-by: Beniamino Galvani <b.galvani@gmail.com> Reviewed-by: Simon Glass <sjg@chromium.org>
* | | arm: implement generic PSCI reset call for armv8Beniamino Galvani2016-05-27-1/+18
|/ / | | | | | | | | | | | | | | | | Add a psci_system_reset() which calls the SYSTEM_RESET function of PSCI 0.2 and can be used by boards that support it to implement reset_cpu(). Signed-off-by: Beniamino Galvani <b.galvani@gmail.com> Reviewed-by: Simon Glass <sjg@chromium.org>
* | sunxi: Increase SPL header size to 64 bytes to avoid code corruptionSiarhei Siamashka2016-05-25-1/+7
| | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | The current SPL header, created by the 'mksunxiboot' tool, has size 32 bytes. But the code in the boot ROM stores the information about the boot media at the offset 0x28 before passing control to the SPL. For example, when booting from the SD card, the magic number written by the boot ROM is 0. And when booting from the SPI flash, the magic number is 3. NAND and eMMC probably have their own special magic numbers too. Currently the corrupted byte is a part of one of the instructions in the reset vectors table: b reset ldr pc, _undefined_instruction ldr pc, _software_interrupt <- Corruption happens here ldr pc, _prefetch_abort ldr pc, _data_abort ldr pc, _not_used ldr pc, _irq ldr pc, _fiq In practice this does not cause any visible problems, but it's still better to fix it. As a bonus, the reported boot media type can be later used in the 'spl_boot_device' function, but this is out of the scope of this patch. Signed-off-by: Siarhei Siamashka <siarhei.siamashka@gmail.com> Reviewed-by: Hans de Goede <hdegoede@redhat.com> Signed-off-by: Hans de Goede <hdegoede@redhat.com>
* | Merge branch 'master' of git://git.denx.de/u-boot-fsl-qoriqTom Rini2016-05-24-10/+34
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| * | driver/ddr/fsl: Add workaround for erratum A-010165Shengzhou Liu2016-05-18-0/+1
| | | | | | | | | | | | | | | | | | | | | | | | | | | During DDR-2133 operation, the transmit data eye margins determined during the memory controller initialization may be sub-optimal, set DEBUG_29[12] and DEBUG_29[13:16] = 4'b0100 before MEM_EN is set. Signed-off-by: Shengzhou Liu <Shengzhou.Liu@nxp.com> Reviewed-by: York Sun <york.sun@nxp.com>
| * | arch/arm, arch/powerpc: add # of SEC engines on the SOCAlex Porosanu2016-05-18-0/+3
| | | | | | | | | | | | | | | | | | | | | | | | | | | | | | Some SOCs, specifically the ones in the C29x familiy can have multiple security engines. This patch adds a system configuration define which indicates the maximum number of SEC engines that can be found on a SoC. Signed-off-by: Alex Porosanu <alexandru.porosanu@nxp.com> Reviewed-by: York Sun <york.sun@nxp.com>
| * | arch/arm: add SEC JR0 offsetAlex Porosanu2016-05-18-10/+28
| | | | | | | | | | | | | | | | | | | | | | | | | | | Freescale PPC SoCs do not hard-code security engine's Job Ring 0 address, rather a define is used. This patch adds the same functionality to the ARM based SoCs (i.e. LS1/LS2 and i.MX parts) Signed-off-by: Alex Porosanu <alexandru.porosanu@nxp.com> Reviewed-by: York Sun <york.sun@nxp.com>
| * | driver/ddr/fsl: Add workaround for erratum A-009801Shengzhou Liu2016-05-17-0/+1
| | | | | | | | | | | | | | | | | | | | | | | | The initial training for the DDRC may provide results that are not optimized. The workaround provides better read timing margins. Signed-off-by: Shengzhou Liu <Shengzhou.Liu@nxp.com> Reviewed-by: York Sun <york.sun@nxp.com>
| * | armv8/ls1043: Add workaround for DDR erratum A-008850Shengzhou Liu2016-05-17-0/+1
| | | | | | | | | | | | | | | | | | | | | | | | | | | Barrier transactions from CCI400 need to be disabled till the DDR is configured, otherwise it may lead to system hang. The patch adds workaround to fix the erratum. Signed-off-by: Shengzhou Liu <Shengzhou.Liu@nxp.com> Reviewed-by: York Sun <york.sun@nxp.com>
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