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| author | Anna, Suman <s-anna@ti.com> | 2016-05-23 13:32:14 -0500 |
|---|---|---|
| committer | Tom Rini <trini@konsulko.com> | 2016-06-02 21:42:16 -0400 |
| commit | 36080228edfdad69299bb6cc2a59ceb17190fcec (patch) | |
| tree | 6f86f163665972b6f22235f1cef1dd592b92a298 /arch/arm/include | |
| parent | 68a775a7665f8cec3c0f6f38179ef5b7eeb2fee0 (diff) | |
| download | u-boot-imx-36080228edfdad69299bb6cc2a59ceb17190fcec.zip u-boot-imx-36080228edfdad69299bb6cc2a59ceb17190fcec.tar.gz u-boot-imx-36080228edfdad69299bb6cc2a59ceb17190fcec.tar.bz2 | |
ARM: DRA7: Update/Correct MPU and CORE OPP_NOM voltage values
The current OPP_NOM voltage values defined for the MPU and CORE
voltage domains are based on the initial DRA75x_74x_SR1.1_DM data
manual. As per this DM, the PMIC boot voltage can be set to either
1.10V or 1.15V for VD_MPU, and either 1.06V or 1.15V for VD_CORE.
While the current values are correct, the latter set of values
are the values that are common across all DRA75x, DRA72x SoCs and
for all current Silicon revisions. So, update both the MPU and CORE
OPP_NOM voltages to 1.15V.
The macros are also slightly reorganized so that both the MPU and
CORE voltage domain values are defined together.
Signed-off-by: Suman Anna <s-anna@ti.com>
Reviewed-by: Lokesh Vutla <lokeshvutla@ti.com>
Diffstat (limited to 'arch/arm/include')
| -rw-r--r-- | arch/arm/include/asm/arch-omap5/clock.h | 8 |
1 files changed, 4 insertions, 4 deletions
diff --git a/arch/arm/include/asm/arch-omap5/clock.h b/arch/arm/include/asm/arch-omap5/clock.h index 38d50d6..9180c67 100644 --- a/arch/arm/include/asm/arch-omap5/clock.h +++ b/arch/arm/include/asm/arch-omap5/clock.h @@ -240,17 +240,17 @@ #define VDD_MM_ES2_LOW 880 /* DRA74x/75x voltage settings in mv for OPP_NOM per DM */ -#define VDD_MPU_DRA752 1100 +#define VDD_MPU_DRA752 1150 +#define VDD_CORE_DRA752 1150 #define VDD_EVE_DRA752 1060 #define VDD_GPU_DRA752 1060 -#define VDD_CORE_DRA752 1060 #define VDD_IVA_DRA752 1060 /* DRA72x voltage settings in mv for OPP_NOM per DM */ -#define VDD_MPU_DRA72x 1100 +#define VDD_MPU_DRA72x 1150 +#define VDD_CORE_DRA72x 1150 #define VDD_EVE_DRA72x 1060 #define VDD_GPU_DRA72x 1060 -#define VDD_CORE_DRA72x 1060 #define VDD_IVA_DRA72x 1060 /* Efuse register offsets for DRA7xx platform */ |