diff options
| author | Lokesh Vutla <lokeshvutla@ti.com> | 2016-05-16 11:47:24 +0530 |
|---|---|---|
| committer | Tom Rini <trini@konsulko.com> | 2016-05-27 15:47:51 -0400 |
| commit | d8ff4fdb103a7964a3351c0b26b256e8ba53319e (patch) | |
| tree | dd21a87fade9689ba152fcaf55eea0a2d834d9cc /arch/arm/include | |
| parent | 866b178bd13639e3960e78acf91ac80a6bd06689 (diff) | |
| download | u-boot-imx-d8ff4fdb103a7964a3351c0b26b256e8ba53319e.zip u-boot-imx-d8ff4fdb103a7964a3351c0b26b256e8ba53319e.tar.gz u-boot-imx-d8ff4fdb103a7964a3351c0b26b256e8ba53319e.tar.bz2 | |
board: AM335x-ICEv2: Add DDR data
AM335x ICEv2 contains a 2Gbit(128Mx16) of DDR3 SDRAM(MT41J128M16JT-125),
capable of running at 400MHz. Adding this specific DDR configuration
details running at 400MHz.
Reviewed-by: Tom Rini <trini@konsulko.com>
Signed-off-by: Lokesh Vutla <lokeshvutla@ti.com>
Diffstat (limited to 'arch/arm/include')
| -rw-r--r-- | arch/arm/include/asm/arch-am33xx/ddr_defs.h | 15 |
1 files changed, 15 insertions, 0 deletions
diff --git a/arch/arm/include/asm/arch-am33xx/ddr_defs.h b/arch/arm/include/asm/arch-am33xx/ddr_defs.h index 97bbfe2..43e122e 100644 --- a/arch/arm/include/asm/arch-am33xx/ddr_defs.h +++ b/arch/arm/include/asm/arch-am33xx/ddr_defs.h @@ -54,6 +54,21 @@ #define MT41J128MJT125_PHY_FIFO_WE 0x100 #define MT41J128MJT125_IOCTRL_VALUE 0x18B +/* Micron MT41J128M16JT-125 at 400MHz*/ +#define MT41J128MJT125_EMIF_READ_LATENCY_400MHz 0x100007 +#define MT41J128MJT125_EMIF_TIM1_400MHz 0x0AAAD4DB +#define MT41J128MJT125_EMIF_TIM2_400MHz 0x26437FDA +#define MT41J128MJT125_EMIF_TIM3_400MHz 0x501F83FF +#define MT41J128MJT125_EMIF_SDCFG_400MHz 0x61C052B2 +#define MT41J128MJT125_EMIF_SDREF_400MHz 0x00000C30 +#define MT41J128MJT125_ZQ_CFG_400MHz 0x50074BE4 +#define MT41J128MJT125_RATIO_400MHz 0x80 +#define MT41J128MJT125_INVERT_CLKOUT_400MHz 0x0 +#define MT41J128MJT125_RD_DQS_400MHz 0x3A +#define MT41J128MJT125_WR_DQS_400MHz 0x3B +#define MT41J128MJT125_PHY_WR_DATA_400MHz 0x76 +#define MT41J128MJT125_PHY_FIFO_WE_400MHz 0x96 + /* Micron MT41K128M16JT-187E */ #define MT41K128MJT187E_EMIF_READ_LATENCY 0x06 #define MT41K128MJT187E_EMIF_TIM1 0x0888B3DB |