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| * | Exynos5: Fix exynos5_get_periph_rate calculationsAkshay Saraswat2015-02-13-8/+13
| | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | exynos5_get_periph_rate function reads incorrect div for SDMMC2 & 3. It also reads prediv and does division only for SDMMC0 & 2 when actually various other peripherals need that. Adding changes to fix these mistakes in periph rate calculation. Signed-off-by: Akshay Saraswat <akshay.s@samsung.com> Reviewed-by: Simon Glass <sjg@chromium.org> Tested-by: Simon Glass <sjg@chromium.org> Signed-off-by: Minkyu Kang <mk7.kang@samsung.com>
| * | Exynos542x: Add and enable get_periph_rate supportAkshay Saraswat2015-02-13-7/+146
| | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | We planned to fetch peripheral rate through one generic API per peripheral. These generic peripheral functions are in turn expected to fetch apt values from a function refactored as per SoC versions. This patch adds support for fetching peripheral rates for Exynos5420 and Exynos5800. Signed-off-by: Akshay Saraswat <akshay.s@samsung.com> Reviewed-by: Simon Glass <sjg@chromium.org> Signed-off-by: Minkyu Kang <mk7.kang@samsung.com>
| * | Exynos542x: Move exynos5420_get_pll_clk up and renameAkshay Saraswat2015-02-13-41/+41
| | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | Moving exynos5420_get_pll_clk function definition up in the code to keep it together with rest of SoC_get_pll_clk functions. This makes code more legible and also removes the need of declaration when called before the position of definition in code. Also, renaming exynos5420_get_pll_clk to exynos542x_get_pll_clk because it is being used for both Exynos 5420 and 5800. Signed-off-by: Akshay Saraswat <akshay.s@samsung.com> Reviewed-by: Simon Glass <sjg@chromium.org> Tested-by: Simon Glass <sjg@chromium.org> Signed-off-by: Minkyu Kang <mk7.kang@samsung.com>
| * | Exynos5: Fix compiler warnings due to clock_get_periph_rateAkshay Saraswat2015-02-13-31/+49
| | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | Apparently, members of clk_bit_info array do not map correctly to the members of enum periph_id. This mapping got broken after we changed periph_id(s) to reflect interrupt number instead of their position in a sequence. This patch intends to fix above mentioned issue. Signed-off-by: Akshay Saraswat <akshay.s@samsung.com> Reviewed-by: Simon Glass <sjg@chromium.org> Tested-by: Simon Glass <sjg@chromium.org> Signed-off-by: Minkyu Kang <mk7.kang@samsung.com>
| * | EXYNOS5: Add function to enable exynos5420 usbdev phy ctrlJoonyoung Shim2015-02-13-2/+26
| | | | | | | | | | | | | | | | | | | | | | | | | | | Exynos5420 has different registers with other exynos5 SoCs to control usb device phy, so need separated function to enable exynos5420 usb device phy. Signed-off-by: Joonyoung Shim <jy0922.shim@samsung.com> Signed-off-by: Minkyu Kang <mk7.kang@samsung.com>
| * | arm: exynos: fix the div value for set_mmc_clkJaehoon Chung2015-02-13-0/+4
| |/ | | | | | | | | | | | | | | | | | | | | The most exynos used the "Ratio + 1" as div value. And value at register is "Ratio". So if want to set exact value, it needs to subtract one. Value at register ("Ratio") = div - 1 Signed-off-by: Jaehoon Chung <jh80.chung@samsung.com> Signed-off-by: Minkyu Kang <mk7.kang@samsung.com>
* | Merge git://git.denx.de/u-boot-dmTom Rini2015-02-13-0/+66
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| * | dm: Kconfig: Move CONFIG_SYS_MALLOC_F_LEN to KconfigSimon Glass2015-02-12-0/+24
| | | | | | | | | | | | | | | Move this option to Kconfig and update all boards. Signed-off-by: Simon Glass <sjg@chromium.org>
| * | dm: omap3: Move driver model CONFIGs to KconfigSimon Glass2015-02-12-0/+9
| | | | | | | | | | | | | | | | | | | | | Remove driver model CONFIGs from the board config headers and use Kconfig instead. Signed-off-by: Simon Glass <sjg@chromium.org>
| * | dm: tegra: Move driver model CONFIGs to KconfigSimon Glass2015-02-12-0/+18
| | | | | | | | | | | | | | | | | | | | | Remove driver model CONFIGs from the board config headers and use Kconfig instead. Signed-off-by: Simon Glass <sjg@chromium.org>
| * | dm: exynos: Move driver model CONFIGs to KconfigSimon Glass2015-02-12-0/+15
| |/ | | | | | | | | | | | | Remove driver model CONFIGs from the board config headers and use Kconfig instead. Signed-off-by: Simon Glass <sjg@chromium.org>
* | Merge branch 'rmobile' of git://git.denx.de/u-boot-shTom Rini2015-02-13-2/+16
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| * arm: rmobile: r8a7794: Enable SMP mode of Auxiliary Control RegisterNobuhiro Iwamatsu2015-02-13-1/+11
| | | | | | | | | | | | | | | | r8a7794 uses ARM SoC of CA7 base. If we want to use dcache on CA7, we need to enable SMP bit of Auxiliary Control Register. Signed-off-by: Nobuhiro Iwamatsu <nobuhiro.iwamatsu.yj@renesas.com> Signed-off-by: Nobuhiro Iwamatsu <iwamatsu@nigauri.org>
| * arm: rmobile: Add SILK board supportVladimir Barinov2015-02-13-1/+5
| | | | | | | | | | | | | | | | | | | | | | SILK is an entry level development board based on R-Car E2 SoC (R8A7794) This commit supports the following peripherals: - SCIF, I2C, Ethernet, QSPI, MMC, USB Host Signed-off-by: Vladimir Barinov <vladimir.barinov@cogentembedded.com> Reviewed-by: Tom Rini <trini@ti.com> Signed-off-by: Nobuhiro Iwamatsu <iwamatsu@nigauri.org>
* | Merge branch 'master' of git://git.denx.de/u-boot-atmelTom Rini2015-02-10-0/+55
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| * | ARM: atmel: sama5d4: add interrupt redirect functionBo Shen2015-02-07-0/+12
| | | | | | | | | | | | | | | | | | Signed-off-by: Bo Shen <voice.shen@atmel.com> [fix subject] Signed-off-by: Andreas Bießmann <andreas.devel@googlemail.com>
| * | ARM: atmel: sama5d4: add bus matrix init functionBo Shen2015-02-07-0/+35
| | | | | | | | | | | | Signed-off-by: Bo Shen <voice.shen@atmel.com>
| * | ARM: atmel: clock: make it possible to configure HMX32Bo Shen2015-02-07-0/+8
| | | | | | | | | | | | Signed-off-by: Bo Shen <voice.shen@atmel.com>
* | | Merge branch 'master' of git://www.denx.de/git/u-boot-imxTom Rini2015-02-10-15/+83
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| * | imx: mx6: Fixed AIPS3 base address issueYe.Li2015-02-10-1/+1
| | | | | | | | | | | | | | | | | | | | | | | | | | | Should use AIPS3 configuration address 0x0227C000 to set AIPS3, not the AIPS3 base address. Additional, replace AIPS1_BASE_ADDR to AIPS3_ARB_BASE_ADDR to align with AIPS1 and AIPS2, and resolve the AIPS3_ARB_BASE_ADDR undefine problem. Signed-off-by: Ye.Li <B37916@freescale.com>
| * | imx:mx6sx add dram io configure for mx6sxPeng Fan2015-01-22-14/+82
| | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | Define two structure mx6sx_iomux_ddr_regs and mx6sx_iomux_grp_regs. Add a new function mx6sx_dram_iocfg to configure dram io. Since mx6sx only have one channel mmdc0, define a new empty macro MMDC1 to replace mmdc1->entry=value for mx6sx. And to other mx6 soc, MMDC1 effects as "mmdc1->entry=value". Signed-off-by: Peng Fan <Peng.Fan@freescale.com>
* | | Merge git://git.denx.de/u-boot-marvellTom Rini2015-02-06-0/+102
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| * | | arm: armada-xp: Add SPL support used to include the DDR training codeStefan Roese2015-02-06-0/+102
| | |/ | |/| | | | | | | | | | | | | | | | | | | | | | | | | This patch adds SPL support to the Marvell Armada-XP. With this addition the bin_hdr integration is not needed any more. The SPL will first initialize the serdes/PHY and the call the DDR setup and training code now integrated into mainline U-Boot. Signed-off-by: Stefan Roese <sr@denx.de> Reviewed-by: Luka Perkov <luka.perkov@sartura.hr>
* | | ARM: UniPhier: leave the last element of boot_device_table emptyMasahiro Yamada2015-02-07-2/+2
| | | | | | | | | | | | | | | | | | | | | | | | Checking if the pointer is NULL would be easier to know the tail of the boot_device_table[] array. For clarification, add the /* sentinel */ comment. Signed-off-by: Masahiro Yamada <yamada.m@jp.panasonic.com>
* | | ARM: UniPhier: refactor pinmon commandMasahiro Yamada2015-02-07-11/+8
| | | | | | | | | | | | | | | | | | | | | | | | | | | | | | The return value of get_boot_mode_sel() is used as the index of the boot_device_table[] array. Its type should be "int" rather than "u32". Use only the iterator "i" for the loop in do_pinmon(). Signed-off-by: Masahiro Yamada <yamada.m@jp.panasonic.com>
* | | ARM: UniPhier: enable I2C input pins for PH1-sLD8Masahiro Yamada2015-02-07-0/+9
| | | | | | | | | | | | | | | | | | | | | To use I2C controllers on PH1-sLD8, the bit 10 (SCL0/SDA0) and bit 11 (SCL1/SDA1) of IECTRL register must be set. Signed-off-by: Masahiro Yamada <yamada.m@jp.panasonic.com>
* | | ARM: UniPhier: do not compile unnecessary objectsMasahiro Yamada2015-02-07-32/+41
| | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | It is true that unused functions are removed from the ELF image by the compiler's garbage collection but relying on it too much does not look nice. Currently, the build is taking more than it should. Refactor the makefiles to compile only files that are really needed. CONFIG_SOC_INIT and CONFIG_DRAM_INIT are no longer needed by the optimization. Signed-off-by: Masahiro Yamada <yamada.m@jp.panasonic.com>
* | | ARM: UniPhier: remove unused checkboard() functionsMasahiro Yamada2015-02-07-51/+0
| | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | Since commit 0365ffcc0bd6 (generic-board: show model name in board_init_f() too), checkboard() is invoked only when show_board_info() fails to get the model name from Device Tree. It never happens because UniPhier SoCs now only work with CONFIG_OF_CONTROL and all the root nodes of UniPhier device trees have the "model" property. Signed-off-by: Masahiro Yamada <yamada.m@jp.panasonic.com>
* | | ARM: UniPhier: revive support card infoMasahiro Yamada2015-02-07-0/+14
| | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | Since commit 0365ffcc0bd6 (generic-board: show model name in board_init_f() too), the support card information has not been displayed because check_support_card() is invoked only when show_board_info() fails to get the model name from Device Tree. This commit adds misc_init_f() function to call check_support_card() from there. Signed-off-by: Masahiro Yamada <yamada.m@jp.panasonic.com>
* | | ARM: UniPhier: move SPL init functions to spl_board_init()Masahiro Yamada2015-02-07-72/+48
| | | | | | | | | | | | | | | | | | | | | | | | Now init functions called from board_postclk_init() and dram_init() are only necessary for SPL. Move them to spl_board_init() for clean-up. Signed-off-by: Masahiro Yamada <yamada.m@jp.panasonic.com>
* | | ARM: UniPhier: move pin_init() to board_early_init_f()Masahiro Yamada2015-02-07-6/+26
|/ / | | | | | | | | | | | | Currently, I/O pin settings are not necessary for SPL. The board_early_init_f() seems a suitable place to call pin_init(). Signed-off-by: Masahiro Yamada <yamada.m@jp.panasonic.com>
* | Merge branch 'master' of git://git.denx.de/u-boot-tiTom Rini2015-02-02-26/+115
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| * | omap3: make SDRC SHARING setting configurableAlbert ARIBAUD \(3ADEV\)2015-01-29-1/+5
| | | | | | | | | | | | Signed-off-by: Albert ARIBAUD (3ADEV) <albert.aribaud@3adev.fr>
| * | omap3: enable GP9 timer and UART2Albert ARIBAUD \(3ADEV\)2015-01-29-0/+9
| | | | | | | | | | | | | | | | | | These are needed for the upcoming Cairo board support. Signed-off-by: Albert ARIBAUD (3ADEV) <albert.aribaud@3adev.fr>
| * | ARM: OMAP5: DRA7xx: Add support for power rail groupingLubomir Popov2015-01-29-25/+101
| | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | On the DRA72x (J6Eco) EVM one PMIC SMPS is powering three SoC core rails. This concept of using one SMPS to supply multiple core domains (in various, although limited combinations, per primary device use case) has now become common and is used by many customer J6/J6Eco designs; it is supported by a number of corresponding PMIC OTP versions. This patch implements correct operation of the core voltages scaling routine by ensuring that each SMPS that is supplying more than one domain shall be written only once, and with the highest voltage of those fused in the SoC (or of those defined in the corresponding header if fuse read is disabled or fails) for the power rails belonging to the group. The patch also replaces some PMIC-related magic numbers with the appropriate definitions. The default OPP_NOM voltages for the DRA7xx SoCs are updated as well, per the latest DMs. Signed-off-by: Lubomir Popov <l-popov@ti.com>
* | | Merge branch 'master' of git://git.denx.de/u-boot-sunxiTom Rini2015-02-02-3/+21
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| * | | sunxi: rsb: Move rsb_set_device_mode() call to rsb_init()Hans de Goede2015-02-02-3/+8
| | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | It turns out that the device_mode_data is rsb specific, rather then slave specific, so integrate the rsb_set_device_mode() call into rsb_init(). Signed-off-by: Hans de Goede <hdegoede@redhat.com> Acked-by: Ian Campbell <ijc@hellion.org.uk>
| * | | sunxi: rsb: Add sun9i (A80 support)Hans de Goede2015-02-02-0/+13
| |/ / | | | | | | | | | | | | | | | | | | Add support for the A80 to the rsb code. Signed-off-by: Hans de Goede <hdegoede@redhat.com> Acked-by: Ian Campbell <ijc@hellion.org.uk>
* | | Merge branch 'master' of git://git.denx.de/u-boot-dmTom Rini2015-01-30-8/+19
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| * | | exynos5: pinmux: check flag for i2c configPrzemyslaw Marczak2015-01-29-8/+19
| |/ / | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | Some versions of Exynos5 supports High-Speed I2C, on few interfaces, this change allows support this. The new flag is: PINMUX_FLAG_HS_MODE Signed-off-by: Przemyslaw Marczak <p.marczak@samsung.com> Cc: Simon Glass <sjg@chromium.org> Cc: Akshay Saraswat <akshay.s@samsung.com> Cc: Minkyu Kang <mk7.kang@samsung.com> Acked-by: Simon Glass <sjg@chromium.org>
* | | ARM: armv7 fix spelling of SCTRLPeng Fan2015-01-30-4/+4
|/ / | | | | | | | | | | | | SCTLR is the abbreviation of System Control Register, so we should use SCTLR but not SCTRL. Signed-off-by: Peng Fan <Peng.Fan@freescale.com>
* | Merge branch 'master' of git://git.denx.de/u-boot-atmelTom Rini2015-01-26-0/+16
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| * | ARM: atmel: sama5d4: add usb device initial codeBo Shen2015-01-19-0/+16
| |/ | | | | | | Signed-off-by: Bo Shen <voice.shen@atmel.com>
* | Merge branch 'zynq' of git://www.denx.de/git/u-boot-microblazeTom Rini2015-01-26-5/+46
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| * | ARM: zynq: List nand, qspi and jtag boot modesMichal Simek2015-01-26-0/+9
| | | | | | | | | | | | | | | | | | Use full boot mode list in SPL. Signed-off-by: Michal Simek <michal.simek@xilinx.com>
| * | ARM: zynq: slcr: Dont modify the reserved bitsSiva Durga Prasad Paladugu2015-01-26-1/+1
| | | | | | | | | | | | | | | | | | | | | | | | | | | | | | Set only the 0-3 bits of the FPGA_RST_CTRL register as other bits should not be set to 1. Signed-off-by: Siva Durga Prasad Paladugu <sivadur@xilinx.com> Reviewed-by: Peter Crosthwaite <peter.crosthwaite@xilinx.com> Reviewed-by: Nathan Rossi <nathan.rossi@xilinx.com> Signed-off-by: Michal Simek <michal.simek@xilinx.com>
| * | ARM: zynq: ddrc: Setup half of memory only for ECC caseMichal Simek2015-01-26-0/+2
| | | | | | | | | | | | | | | | | | | | | | | | | | | Setup half of memory from ram_size for ECC case. All the time the same board can be configured with or without ECC. Based on ECC case detection use half of memory with the same configuration. Signed-off-by: Michal Simek <michal.simek@xilinx.com>
| * | ARM: zynq: Remove empty lineMichal Simek2015-01-26-1/+0
| | | | | | | | | | | | | | | | | | Trivial patch. Signed-off-by: Michal Simek <michal.simek@xilinx.com>
| * | ARM: zynq: Enable the Neon instructionsMichal Simek2015-01-26-3/+34
| | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | Added the lowlevel_init to enable the Neon instructions. Initially the u-boot was causing undefined instruction exception if loaded through tcl, and working fine if loaded through FSBL. The exception was causing in convertion formula of given time to ticks. It was because, the Neon instructions were disabled and hence causing the undefined exception. In FSBL case, the FSBL was enabling the Neon instructions. Hence, added the lowlevel_init to enable the Neon instructions. Also enable neon instructions for non-xilinx toolchain. Signed-off-by: Siva Durga Prasad Paladugu <sivadur@xilinx.com> Acked-by: Radhey Shyam Pandey <radheys@xilinx.com> Signed-off-by: Michal Simek <michal.simek@xilinx.com>
* | | fsl/ls1021qds: Add deep sleep supporttang yuantian2015-01-24-0/+19
| | | | | | | | | | | | | | | | | | | | | | | | Add deep sleep support on Freescale LS1021QDS platform. Signed-off-by: Tang Yuantian <Yuantian.Tang@freescale.com> [York Sun: Fix conflict in fdt.c] Reviewed-by: York Sun <yorksun@freescale.com>
generated by cgit v1.1 at 2024-10-11 03:20:21 +0000