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| author | Akshay Saraswat <akshay.s@samsung.com> | 2015-02-04 16:00:02 +0530 |
|---|---|---|
| committer | Minkyu Kang <mk7.kang@samsung.com> | 2015-02-13 17:23:06 +0900 |
| commit | 9deff107468ac6d80db962470796e05c667c1077 (patch) | |
| tree | 9d058dd9a5dea7a71ccf007415ced631796be486 /arch/arm/cpu/armv7 | |
| parent | ecdfb4e9d2e2bd691e94ee8f96da2e8d7dc45e81 (diff) | |
| download | u-boot-imx-9deff107468ac6d80db962470796e05c667c1077.zip u-boot-imx-9deff107468ac6d80db962470796e05c667c1077.tar.gz u-boot-imx-9deff107468ac6d80db962470796e05c667c1077.tar.bz2 | |
Exynos5: Fix exynos5_get_periph_rate calculations
exynos5_get_periph_rate function reads incorrect div for
SDMMC2 & 3. It also reads prediv and does division only for
SDMMC0 & 2 when actually various other peripherals need that.
Adding changes to fix these mistakes in periph rate calculation.
Signed-off-by: Akshay Saraswat <akshay.s@samsung.com>
Reviewed-by: Simon Glass <sjg@chromium.org>
Tested-by: Simon Glass <sjg@chromium.org>
Signed-off-by: Minkyu Kang <mk7.kang@samsung.com>
Diffstat (limited to 'arch/arm/cpu/armv7')
| -rw-r--r-- | arch/arm/cpu/armv7/exynos/clock.c | 21 |
1 files changed, 13 insertions, 8 deletions
diff --git a/arch/arm/cpu/armv7/exynos/clock.c b/arch/arm/cpu/armv7/exynos/clock.c index 59d7dc8..0153314 100644 --- a/arch/arm/cpu/armv7/exynos/clock.c +++ b/arch/arm/cpu/armv7/exynos/clock.c @@ -362,8 +362,8 @@ static struct clk_bit_info *get_clk_bit_info(int peripheral) static unsigned long exynos5_get_periph_rate(int peripheral) { struct clk_bit_info *bit_info = get_clk_bit_info(peripheral); - unsigned long sclk, sub_clk; - unsigned int src, div, sub_div; + unsigned long sclk, sub_clk = 0; + unsigned int src, div, sub_div = 0; struct exynos5_clock *clk = (struct exynos5_clock *)samsung_get_base_clock(); @@ -402,10 +402,13 @@ static unsigned long exynos5_get_periph_rate(int peripheral) break; case PERIPH_ID_SDMMC0: case PERIPH_ID_SDMMC1: + src = readl(&clk->src_fsys); + div = readl(&clk->div_fsys1); + break; case PERIPH_ID_SDMMC2: case PERIPH_ID_SDMMC3: src = readl(&clk->src_fsys); - div = readl(&clk->div_fsys1); + div = readl(&clk->div_fsys2); break; case PERIPH_ID_I2C0: case PERIPH_ID_I2C1: @@ -426,7 +429,8 @@ static unsigned long exynos5_get_periph_rate(int peripheral) return -1; }; - src = (src >> bit_info->src_bit) & 0xf; + if (bit_info->src_bit >= 0) + src = (src >> bit_info->src_bit) & 0xf; switch (src) { case EXYNOS_SRC_MPLL: @@ -443,11 +447,12 @@ static unsigned long exynos5_get_periph_rate(int peripheral) } /* Ratio clock division for this peripheral */ - sub_div = (div >> bit_info->div_bit) & 0xf; - sub_clk = sclk / (sub_div + 1); + if (bit_info->div_bit >= 0) { + sub_div = (div >> bit_info->div_bit) & 0xf; + sub_clk = sclk / (sub_div + 1); + } - /* Pre-ratio clock division for SDMMC0 and 2 */ - if (peripheral == PERIPH_ID_SDMMC0 || peripheral == PERIPH_ID_SDMMC2) { + if (bit_info->prediv_bit >= 0) { div = (div >> bit_info->prediv_bit) & 0xff; return sub_clk / (div + 1); } |