| Commit message (Collapse) | Author | Age | Lines |
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The mx6sx sabreauto boards uses 2G DDR3. Modify the configuration
PHYS_SDRAM_SIZE to this size.
Signed-off-by: Ye.Li <B37916@freescale.com>
Acked-by: Jason Liu
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Create mx6sx sabreauto BSP file and configurations. The devices below
have been supported:
1. SD/MMC/eMMC on SDA/SDB (base board) sockets
2. USB OTG port and USB HOST port (base board)
3. NAND flash
4. QuadSPI flash on QSPI1
5. I2C
6. PMIC PFUZE100
7. Onboard ethernet chip on ENET2
8. Splash screen on LVDS
Signed-off-by: Ye.Li <B37916@freescale.com>
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Add support for i.MX6SX 14x14 lpddr2 arm2 board, same
as 17x17 arm2 except lpddr2 instead of ddr3.
Signed-off-by: Nitin Garg <nitin.garg@freescale.com>
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Currently, flash quad bit is set in "spi_flash_validate_params" and later
at the end in the same api, we write 0 to status register for few flashes,
thereby overriding the quad bit set. This fix moves the quad bit setting
outside this api in "spi_flash_probe_slave"
Signed-off-by: Sourav Poddar <sourav.poddar@ti.com>
Reviewed-by: Jagannadha Sutradharudu Teki <jaganna@xilinx.com>
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ROM fixes the WEIM plugin issue in TO 1.2. The work around for hacking WEIM base
address to ROM variable is not needed. To avoid hacking useful data, remove the
work around for TO 1.2 and higher revisions.
Signed-off-by: Ye.Li <B37916@freescale.com>
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As M4 is sourcing UART clk from OSC, to make UART work
when M4 is enabled, need to select OSC as clk parent,
24M OSC is enough for debug UART in uboot.
Signed-off-by: Anson Huang <b20788@freescale.com>
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Set the CONFIG_MXC_GPT_HCLK configuration in mx6_common.h, so that
enable the 24Mhz OSC GPT on all MX6 platforms.
Signed-off-by: Ye.Li <B37916@freescale.com>
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For MX6SL, uses the OSC 24Mhz as the preclk source in CCM. Align the
preclk setting with kernel.
Signed-off-by: Ye.Li <B37916@freescale.com>
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For MX6SL and MX6SX, the perclk can come from OSC 24Mhz source. Fix
the get_ipg_per_clk function to support it.
Signed-off-by: Ye.Li <B37916@freescale.com>
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The MX6SL has the perclk_clk_sel to select the perclk source. Add
its define in CCM
Signed-off-by: Ye.Li <B37916@freescale.com>
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Introduce a new configuration "CONFIG_MXC_GPT_HCLK". When it is set,
the GPT will use 24Mhz OSC as clock source. Otherwise, the GPT will
use 32Khz OSC as clock source.
Since only the GPT on iMX6 series provide the clock source option for
24Mhz OSC. For other series(MX5), if the configuration is set, the
perclk will be selected as clock source.
MX6Q/D Rev 1.0 and MX6SL can't use the 24Mhz OSC clock source option,
so select the perclk for them. For MX6SL, we will set the OSC 24Mhz to
perclk in CCM, so eventually the clock comes from OSC 24Mhz.
Signed-off-by: Ye.Li <B37916@freescale.com>
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after boot.
The self-bias circuit is used by the bandgap during startup.
Once the bandgap has stabilized, the self-bias circuit should be
disabled for best noise performance of analog blocks.
Also this bit should be disabled before the chip enters STOP mode or
when ever the regular bandgap is disabled.
Signed-off-by: Ranjani Vaidyanathan <Ranjani.Vaidyanathan@freescale.com>
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THe anatop registers structure is duplicated with CCM structure at
PLL fields.
Since we are suggested not to use the name "anatop" any longer, merge
the anatop registers to the CCM structure "mxc_ccm_reg" and use CCM
to replace anatop.
Signed-off-by: Ye.Li <B37916@freescale.com>
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This problem is found when debugging QuadSPI. When "A" bit is enabled,
unaligned access will cause data abort exception. Actually, we do not
want this exception. So clear the align bit for MX6 SOCs.
Tested this code with android team colleague and did not find problem.
Signed-off-by: Peng Fan <Peng.Fan@freescale.com>
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To fsl_qspi_write_data and fsl_qspi_ip_read, pointer txbuf and
rxbuf are not guaranteed that they are 4 Bytes aligned. Also,
it it not a good idea to cast type 'u8 *' to 'u32 *', except
we are sure that pointer type 'u8 *' is 4 Bytes aligned and
cast it to 'u32 *' will not pass memory boundary.
The problem is found when using fsl_qspi_write_data to write
registers in flash devices. The err msg:
data abort
pc : [<87822f44>] lr : [<87822f38>]
sp : bf5512c8 ip : 0000001c fp : bf856608
r10: 87868904 r9 : bf551efc r8 : 200f048c
r7 : 00000002 r6 : bf551336 r5 : bf552a70 r4 : 00000001
r3 : 00000000 r2 : 00000060 r1 : 8783b520 r0 : 8783b520
Flags: nZCv IRQs on FIQs off Mode SVC_32
Resetting CPU ...
The asm code which cause data abort is:
87822f30: e5964000 ldr r4, [r6]
From the dump msg, r6 is not 4 Bytes aligned, and data abort exception.
So, Use mempcy but not unsafe type casting.
In this patch, max_write_size is assigned using txfifo to avoid possible
errors in future.
Signed-off-by: Peng Fan <Peng.Fan@freescale.com>
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Couple of issues in commit 21a2eb5f. The RAM size is wrong and
max number of DCD is 220.
Signed-off-by: Nitin Garg <nitin.garg@freescale.com>
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The QSPI clock rate was set without disabling the clock gate, the
randomly glitch may mess up the clock and there will be no clock output,
when kernel boot up the QSPI access will fail.
To debug this issueon i.MX6SX SDB, changed the u-boot bootscript to 'sf probe; reset'
to keep rebooting, the issue can be reproduced in 20 mins, set clock out
register in CCM and measured TP86, found there is no clock ouput.
To fix this bug, disable clock gate before changing clock rate.
NOTICE: QSPI2 and GPMI_BCH_INPUT_GPMI_IO share the same clock gate, need
to disable both of them.
Signed-off-by: Allen Xu <b45815@freescale.com>
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WDZST bit is write-once only bit. So we need take care the setting
in kernel ,otherwise, kernel setting will never be enabled.
Signed-off-by: Robin Gong <b38343@freescale.com>
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Add support for i.MX6DQ/DL arm2 LPDDR2 boards.
Signed-off-by: Nitin Garg <nitin.garg@freescale.com>
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In ldo-bypass mode, we need trigger WDOG_B pin to reset pmic in ldo-bypass mode.
Signed-off-by: Robin Gong <b38343@freescale.com>
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Current only set VDDARM_IN@1.175V/VDDSOC_IN@1.175V before ldo bypass switch.
So untile ldo bypass switch happened, these voltage setting is set in ldo-enable
mode. But in datasheet, we need 1.15V + 125mV = 1.275V for VDDARM_IN. We need
to downgrade cpufreq to 400Mhz and restore after ldo bypass mode switch.
Signed-off-by: Robin Gong <b38343@freescale.com>
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From i2c spec, if device pull down the SDA line that causes
i2c bus dead, host can send out 9 clock to let device release
SDA.
But for some special device like pfuze100, it pull down SDA line
and the solution cannot take effort.
The patch just add NACK and STOP signal after 8 dummy clock, and pmic
can release SDA line after the recovery. Test case catch 375 times of
i2c hang, and all are recovered.
Signed-off-by: Fugang Duan <B38611@freescale.com>
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u-boot v2014 upstream codes have a problem in pfd reset (s_init function)
that imx6 Dual is not applied for PLL2 PFD2 reset. It is originated by
using dynamical cpu type checking and introducing two cpu types:
MXC_CPU_MX6Q and MXC_CPU_MX6D for iMX6 Dual/Quad platform.
Fixed this problem by checking the pre_periph_clk_sel and pre_periph2_clk
of CCM CBCMR register, if the PLL2 PFD0 or PLL2 PFD2 is used for the clock
source, do not reset this PFD to avoid system hang.
Signed-off-by: Ye.Li <B37916@freescale.com>
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Correct the wrong setting, otherwise, i2c recovery code will use
the wrong scl pin to recove, and will never recovery successfully.
Signed-off-by: Robin Gong <b38343@freescale.com>
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The BOOTCFG value used by bmode for SABRESD eMMC are actually for SD card.
Fixed the value to correct one.
Signed-off-by: Ye.Li <B37916@freescale.com>
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HWApps team updates iMX6SX 19x19 validation board LPDDR2 script.
This script is JEDEC compliant.
http://compass.freescale.net/livelink/livelink/open/232537085
Update the LPDDR2 settings in DCD and plugin.
Signed-off-by: Ye.Li <B37916@freescale.com>
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Let's use the i.MX common miscellaneous reset API
to reset the LCDIF block so that we may eliminate
a random hang issue at the arch_preboot_os() stage
when we disable the LCDIF. This patch also waits
for a VSYNC interrupt to guarantee the reset is
done at the VSYNC edge, which somehow makes the
LCDIF consume the display FIFO(?) and helps the
LCDIF work normally at the kernel stage.
Tested-by: Jason Liu <r64343@freescale.com>
Tested-by: Sandor Yu <R01008@freescale.com>
Tested-by: Ye.Li <B37916@freescale.com>
Tested-by: Guo Sally <b38912@freescale.com>
Signed-off-by: Liu Ying <Ying.Liu@freescale.com>
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Enable pcie support in uboot on imx6sx sd boards
- enable_pcie_clock should be call before ssp_en is set,
since that ssp_en control the phy_ref clk gate, turn on
it after the source of the pcie clks are stable.
- add debug info
- add rx_eq of gpr12 on imx6sx
- there are random link down issue on imx6sx. It's
pcie ep reset issue.
solution:reset ep, then retry link can fix it.
Signed-off-by: Richard Zhu <r65037@freescale.com>
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set console value to show download log info for mfgtool NAND download.
Signed-off-by: Allen Xu <b45815@freescale.com>
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Since QSPI will be disabled for NAND module(pin conflict), the mtd
partition number will be count from 0, the last partition for rootfs
need to be changed from 4 to 3.
Signed-off-by: Allen Xu <b45815@freescale.com>
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imx6 q/dl/solo pcie would be failed to work properly in kernel, if
the pcie module is iniialized/enumerated both in uboot and linux
kernel.
rootcause:imx6 q/dl/solo pcie don't have the reset mechanism.
it is only be RESET by the POR. So, the pcie module only be
initialized/enumerated once in one POR.
Set to use pcie in kernel defaultly, mask the pcie config here.
Remove the mask freely, if the uboot pcie functions, rather than
the kernel's, are required.
Signed-off-by: Richard Zhu <r65037@freescale.com>
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The iMX6SX SABRESD RevB board uses Micron N25Q128 to replace Spansion S25FL128
on RevA board.
So enable the CONFIG_SPI_FLASH_STMICRO and CONFIG_SPI_FLASH_SPANSION to support
both two revisions.
Signed-off-by: Ye.Li <B37916@freescale.com>
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Add new function "arch_auxiliary_core_check_up" to check whether M4
is already up. Therefore, avoid starting M4 again when it is running.
Signed-off-by: Ye.Li <B37916@freescale.com>
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The mxc gis driver should not disable mxsfb, instead,
mxsfb could be disabled in machine layer.
Signed-off-by: Liu Ying <Ying.Liu@freescale.com>
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The kernel may break the display pipeline at boot stage and
introduce various display artifacts, so let's disable mxsfb
in uboot when necessary.
Signed-off-by: Liu Ying <Ying.Liu@freescale.com>
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DIV_SELECT is used as Fout = Fin * div_select / 2.0, so we should do
the shift after the multiply to avoid rounding errors
Signed-off-by: Andre Renaud <andre@bluewatersys.com>
(cherry picked from commit 2eb268f6fd236a5ad9d51e7e47190d7994b3920f)
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Commit 3d622b78 (mx6: soc: Introduce set_ldo_voltage()) introduces
set_ldo_voltage() function that can be used to set the voltages
of any of the three LDO regulators controlled by the PMU_REG_CORE register.
Prior to this commit there was a single set_vddsoc() which only configured the
VDDSOC regulator.
Update the comments to align with the new set_ldo_voltage() implementation.
Acked-by: Jason Liu <r64343@freescale.com>
Signed-off-by: Fabio Estevam <fabio.estevam@freescale.com>
(cherry picked from commit 157f45da91b306d71dbf3a51325352dc11bf16d1)
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Vadc need long time to auto standards detection,
the default standard is NTSC, if vadc connect to PAL
camera and no enough time to detect the video mode,
driver will get wrong standard.
Confirmation from chip design architecture that auto detect function
is not required by rear-view camera application.
Setting register vdec_stddbg standard_filte bits to 0
makes the standard detection faster, the issue duplicate
decrease to 1%.
Signed-off-by: Sandor Yu <R01008@freescale.com>
(cherry picked from commit 06735bf6724f2dad2dcbbfc188c6a17145c7126b)
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When booting from NAND, the memory copy to boothdr uses the size
of fastboot_boot_img_hdr structure which is actually larger than
boothdr size. This causes the u-boot heap corruption and failed
to allocate memory any more.
Signed-off-by: Ye.Li <B37916@freescale.com>
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GIS module need about 3M+3M+1.5M+1.5M=9M memory.
When gis module enabled, malloc may failed to allocate memory
for other modules, that may cause system hang.
Expand malloc pool to 32M, system hang issue can not duplicate
on mx6sx arm2 board.
pass one night reset stress test.
Signed-off-by: Sandor Yu <R01008@freescale.com>
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When gis enable in uboot, the CSI0 input mux select setting
to vadc module, clean the bit when gis disabled.
Signed-off-by: Sandor Yu <R01008@freescale.com>
(cherry picked from commit ae66b17b7da3be50dc81ca636b67e8e879f52e26)
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Android supports to two ways to pass serialno:
1. ATAG_SERIAL
2. "androidboot.serialno=" argument in boot commandline.
Since we support the DTB for android, so the ATAGS can't work. We have to choose
the second way.
This patch only applys the bootargs in bootimg, while the bootargs saved in u-boot
env variables won't have this argument appended.
Signed-off-by: Ye.Li <B37916@freescale.com>
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The android boot needs get_board_serial function to get the
CPU uid as the serial number. Implement this function to read
the uid from fuse for all iMX6 platforms.
Signed-off-by: Ye.Li <B37916@freescale.com>
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The v2014 u-boot provides some “mmc” sub-commands for setting eMMC
boot parameters, such as boot bus, partition, etc.
These sub-commands are controlled by "CONFIG_SUPPORT_EMMC_BOOT".
Enable this configuration for iMX6SXSABRESD board.
Signed-off-by: Ye.Li <B37916@freescale.com>
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The mtest is no longer default in v2014.
To test the DDR, enable this command for each iMX6 board.
Signed-off-by: Ye.Li <B37916@freescale.com>
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Align the keymap with Android rootfs as:
FUNC1 -- > Volume +
FUNC2 -- > Volume -
Signed-off-by: guoyin.chen <guoyin.chen@freescale.com>
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The kernel changes to fix the mmcblk index with USDHC controllers
as below:
mmcblk0 ---> USDHC1
mmcblk1 ---> USDHC2
mmcblk2 ---> USDHC3
mmcblk3 ---> USDHC4
So in u-boot, the "mmcroot" must be updated together.
When booting from SD/MMC device, change the "mmcroot" to
dynamically set according to the boot USDHC controller.
It is the same mechanism as "mmcdev" used for kernel image loading.
Therefore, the uboot, kernel image, dtb and rootfs are required
in same SD/MMC card.
To disable the mmc dynamical detection, set the "mmcautodetect" to "no",
then "mmcroot" and "mmcdev" will not be overwritten.
When booting from other devices which needs to load kernel, dtb and
rootfs from SD/MMC card, their "mmcdev" reset vaule is
CONFIG_SYS_MMC_ENV_DEV and "mmcroot" reset value is CONFIG_MMCROOT.
Signed-off-by: Ye.Li <B37916@freescale.com>
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Since the iMX6SL does not have PCIE module, should not define the
function "imx_set_pcie_phy_power_down" for it. Otherwise, get the
build warning below:
arch/arm/cpu/armv7/mx6/soc.c:446:13: warning: 'imx_set_pcie_phy_power_down'
defined but not used [-Wunused-function]
static void imx_set_pcie_phy_power_down(void)
Signed-off-by: Ye.Li <B37916@freescale.com>
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Update latest DDR3 scirpts for imx6sx SabreSD and 19x19 DDR3 ARM2 board
as provided by board team.
(http://sw-git.freescale.net/cgi-bin/gitweb.cgi?p=ddr-scripts-rel.git)
Signed-off-by: Ye.Li <B37916@freescale.com>
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The NOR flash PC28F00AG18 has 512 of 256KB erase blocks which are
locked after power on reset. Change the 17x17 ARM2 configurations
to match the flash parameters, and enable the CONFIG_SYS_FLASH_PROTECTION
to allow write to the flash.
The EIM-NOR on 17x17 ARM2 board uses MUXed mode. This has less
effort on board rework.
When boot from EIM-NOR, set SW8, SW7, SW5 to all off.
Signed-off-by: Ye.Li <B37916@freescale.com>
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