ENGR00330792 imx: mx6: Merge anatop registers to CCM structure

THe anatop registers structure is duplicated with CCM structure at
PLL fields.
Since we are suggested not to use the name "anatop" any longer, merge
the anatop registers to the CCM structure "mxc_ccm_reg" and use CCM
to replace anatop.

Signed-off-by: Ye.Li <B37916@freescale.com>

7 files changed, 160 insertions, 216 deletions

diff --git a/arch/arm/cpu/armv7/mx6/clock.c b/arch/arm/cpu/armv7/mx6/clock.c
index af92a17..0c6abbc 100644
--- a/arch/arm/cpu/armv7/mx6/clock.c
+++ b/arch/arm/cpu/armv7/mx6/clock.c
@@ -608,13 +608,10 @@ int enable_fec_anatop_clock(int fec_id, enum enet_freq freq)
 	u32 reg = 0;
 	s32 timeout = 100000;
 
-	struct anatop_regs __iomem *anatop =
-		(struct anatop_regs __iomem *)ANATOP_BASE_ADDR;
-
 	if (freq < ENET_25MHz || freq > ENET_125MHz)
 		return -EINVAL;
 
-	reg = readl(&anatop->pll_enet);
+	reg = readl(&imx_ccm->analog_pll_enet);
 	reg &= ~BM_ANADIG_PLL_ENET_DIV_SELECT;
 
 	if (0 == fec_id) {
@@ -628,9 +625,9 @@ int enable_fec_anatop_clock(int fec_id, enum enet_freq freq)
 	if ((reg & BM_ANADIG_PLL_ENET_POWERDOWN) ||
 	    (!(reg & BM_ANADIG_PLL_ENET_LOCK))) {
 		reg &= ~BM_ANADIG_PLL_ENET_POWERDOWN;
-		writel(reg, &anatop->pll_enet);
+		writel(reg, &imx_ccm->analog_pll_enet);
 		while (timeout--) {
-			if (readl(&anatop->pll_enet) & BM_ANADIG_PLL_ENET_LOCK)
+			if (readl(&imx_ccm->analog_pll_enet) & BM_ANADIG_PLL_ENET_LOCK)
 				break;
 		}
 		if (timeout < 0)
@@ -646,7 +643,7 @@ int enable_fec_anatop_clock(int fec_id, enum enet_freq freq)
 #ifdef CONFIG_FEC_MXC_25M_REF_CLK
 	reg |= BM_ANADIG_PLL_ENET_REF_25M_ENABLE;
 #endif
-	writel(reg, &anatop->pll_enet);
+	writel(reg, &imx_ccm->analog_pll_enet);
 
 	return 0;
 }
@@ -769,12 +766,8 @@ int enable_sata_clock(void)
 
 int enable_pcie_clock(void)
 {
-	struct anatop_regs *anatop_regs =
-		(struct anatop_regs *)ANATOP_BASE_ADDR;
-	struct mxc_ccm_reg *ccm_regs = (struct mxc_ccm_reg *)CCM_BASE_ADDR;
-
 	/* PCIe reference clock sourced from AXI. */
-	clrbits_le32(&ccm_regs->cbcmr, MXC_CCM_CBCMR_PCIE_AXI_CLK_SEL);
+	clrbits_le32(&imx_ccm->cbcmr, MXC_CCM_CBCMR_PCIE_AXI_CLK_SEL);
 
 	/*
 	 * Here be dragons!
@@ -793,7 +786,7 @@ int enable_pcie_clock(void)
 #define ANADIG_ANA_MISC1_LVDS1_CLK_SEL_MASK	0x0000001F
 #ifndef CONFIG_MX6SX
 	/* lvds_clk1 is sourced from sata ref on imx6q/dl/solo */
-	clrsetbits_le32(&anatop_regs->ana_misc1,
+	clrsetbits_le32(&imx_ccm->ana_misc1,
 			ANADIG_ANA_MISC1_LVDSCLK1_IBEN |
 			ANADIG_ANA_MISC1_LVDS1_CLK_SEL_MASK,
 			ANADIG_ANA_MISC1_LVDSCLK1_OBEN | 0xb);
@@ -806,7 +799,7 @@ int enable_pcie_clock(void)
 			BM_ANADIG_PLL_ENET_ENABLE_PCIE);
 #else
 	/* lvds_clk1 is sourced from pcie ref on imx6sx */
-	clrsetbits_le32(&anatop_regs->ana_misc1,
+	clrsetbits_le32(&imx_ccm->ana_misc1,
 			ANADIG_ANA_MISC1_LVDSCLK1_IBEN |
 			ANADIG_ANA_MISC1_LVDS1_CLK_SEL_MASK,
 			ANADIG_ANA_MISC1_LVDSCLK1_OBEN | 0xa);
diff --git a/arch/arm/cpu/armv7/mx6/soc.c b/arch/arm/cpu/armv7/mx6/soc.c
index 2fae6f4..a9b38cc 100644
--- a/arch/arm/cpu/armv7/mx6/soc.c
+++ b/arch/arm/cpu/armv7/mx6/soc.c
@@ -59,12 +59,12 @@ static unsigned int fuse = ~0;
 
 u32 get_cpu_rev(void)
 {
-	struct anatop_regs *anatop = (struct anatop_regs *)ANATOP_BASE_ADDR;
-	u32 reg = readl(&anatop->digprog_sololite);
+	struct mxc_ccm_reg *ccm_regs = (struct mxc_ccm_reg *)CCM_BASE_ADDR;
+	u32 reg = readl(&ccm_regs->digprog_sololite);
 	u32 type = ((reg >> 16) & 0xff);
 
 	if (type != MXC_CPU_MX6SL) {
-		reg = readl(&anatop->digprog);
+		reg = readl(&ccm_regs->digprog);
 		struct scu_regs *scu = (struct scu_regs *)SCU_BASE_ADDR;
 		u32 cfg = readl(&scu->config) & 3;
 		type = ((reg >> 16) & 0xff);
@@ -159,16 +159,16 @@ void init_aips(void)
 
 static void clear_ldo_ramp(void)
 {
-	struct anatop_regs *anatop = (struct anatop_regs *)ANATOP_BASE_ADDR;
+	struct mxc_ccm_reg *ccm_regs = (struct mxc_ccm_reg *)CCM_BASE_ADDR;
 	int reg;
 
 	/* ROM may modify LDO ramp up time according to fuse setting, so in
 	 * order to be in the safe side we neeed to reset these settings to
 	 * match the reset value: 0'b00
 	 */
-	reg = readl(&anatop->ana_misc2);
+	reg = readl(&ccm_regs->ana_misc2);
 	reg &= ~(0x3f << 24);
-	writel(reg, &anatop->ana_misc2);
+	writel(reg, &ccm_regs->ana_misc2);
 }
 
 /*
@@ -180,8 +180,8 @@ static void clear_ldo_ramp(void)
  */
 static int set_ldo_voltage(enum ldo_reg ldo, u32 mv)
 {
-	struct anatop_regs *anatop = (struct anatop_regs *)ANATOP_BASE_ADDR;
-	u32 val, step, old, reg = readl(&anatop->reg_core);
+	struct mxc_ccm_reg *ccm_regs = (struct mxc_ccm_reg *)CCM_BASE_ADDR;
+	u32 val, step, old, reg = readl(&ccm_regs->reg_core);
 	u8 shift;
 
 	if (mv < 725)
@@ -213,7 +213,7 @@ static int set_ldo_voltage(enum ldo_reg ldo, u32 mv)
 		return 0;
 
 	reg = (reg & ~(0x1F << shift)) | (val << shift);
-	writel(reg, &anatop->reg_core);
+	writel(reg, &ccm_regs->reg_core);
 
 	/*
 	 * The LDO ramp-up is based on 64 clock cycles of 24 MHz = 2.6 us per
@@ -240,7 +240,6 @@ static int read_cpu_temperature(void)
 	unsigned int ccm_ccgr2;
 	unsigned int reg, tmp;
 	unsigned int raw_25c, raw_n40c, ratio;
-	struct anatop_regs *anatop = (struct anatop_regs *)ANATOP_BASE_ADDR;
 	struct mxc_ccm_reg *mxc_ccm = (struct mxc_ccm_reg *)CCM_BASE_ADDR;
 	struct ocotp_regs *ocotp = (struct ocotp_regs *)OCOTP_BASE_ADDR;
 	struct fuse_bank *bank = &ocotp->bank[1];
@@ -248,22 +247,22 @@ static int read_cpu_temperature(void)
 			(struct fuse_bank1_regs *)bank->fuse_regs;
 
 	/* need to make sure pll3 is enabled for thermal sensor */
-	if ((readl(&anatop->usb1_pll_480_ctrl) &
+	if ((readl(&mxc_ccm->analog_usb1_pll_480_ctrl) &
 			BM_ANADIG_USB1_PLL_480_CTRL_LOCK) == 0) {
 		/* enable pll's power */
 		writel(BM_ANADIG_USB1_PLL_480_CTRL_POWER,
-				&anatop->usb1_pll_480_ctrl_set);
-		writel(0x80, &anatop->ana_misc2_clr);
+				&mxc_ccm->analog_usb1_pll_480_ctrl_set);
+		writel(0x80, &mxc_ccm->ana_misc2_clr);
 		/* wait for pll lock */
-		while ((readl(&anatop->usb1_pll_480_ctrl) &
+		while ((readl(&mxc_ccm->analog_usb1_pll_480_ctrl) &
 			BM_ANADIG_USB1_PLL_480_CTRL_LOCK) == 0)
 			;
 		/* disable bypass */
 		writel(BM_ANADIG_USB1_PLL_480_CTRL_BYPASS,
-				&anatop->usb1_pll_480_ctrl_clr);
+				&mxc_ccm->analog_usb1_pll_480_ctrl_clr);
 		/* enable pll output */
 		writel(BM_ANADIG_USB1_PLL_480_CTRL_ENABLE,
-				&anatop->usb1_pll_480_ctrl_set);
+				&mxc_ccm->analog_usb1_pll_480_ctrl_set);
 	}
 
 	ccm_ccgr2 = readl(&mxc_ccm->CCGR2);
@@ -303,35 +302,35 @@ static int read_cpu_temperature(void)
 	 * the temperature, we will power on/down anadig thermal
 	 * module
 	 */
-	writel(BM_ANADIG_TEMPSENSE0_POWER_DOWN, &anatop->tempsense0_clr);
-	writel(BM_ANADIG_ANA_MISC0_REFTOP_SELBIASOFF, &anatop->ana_misc0_set);
+	writel(BM_ANADIG_TEMPSENSE0_POWER_DOWN, &mxc_ccm->tempsense0_clr);
+	writel(BM_ANADIG_ANA_MISC0_REFTOP_SELBIASOFF, &mxc_ccm->ana_misc0_set);
 
 	/* write measure freq */
-	reg = readl(&anatop->tempsense1);
+	reg = readl(&mxc_ccm->tempsense1);
 	reg &= ~BM_ANADIG_TEMPSENSE1_MEASURE_FREQ;
 	reg |= MEASURE_FREQ;
-	writel(reg, &anatop->tempsense1);
+	writel(reg, &mxc_ccm->tempsense1);
 
-	writel(BM_ANADIG_TEMPSENSE0_MEASURE_TEMP, &anatop->tempsense0_clr);
-	writel(BM_ANADIG_TEMPSENSE0_FINISHED, &anatop->tempsense0_clr);
-	writel(BM_ANADIG_TEMPSENSE0_MEASURE_TEMP, &anatop->tempsense0_set);
+	writel(BM_ANADIG_TEMPSENSE0_MEASURE_TEMP, &mxc_ccm->tempsense0_clr);
+	writel(BM_ANADIG_TEMPSENSE0_FINISHED, &mxc_ccm->tempsense0_clr);
+	writel(BM_ANADIG_TEMPSENSE0_MEASURE_TEMP, &mxc_ccm->tempsense0_set);
 
-	while ((readl(&anatop->tempsense0) &
+	while ((readl(&mxc_ccm->tempsense0) &
 			BM_ANADIG_TEMPSENSE0_FINISHED) == 0)
 		udelay(10000);
 
-	reg = readl(&anatop->tempsense0);
+	reg = readl(&mxc_ccm->tempsense0);
 	tmp = (reg & BM_ANADIG_TEMPSENSE0_TEMP_VALUE)
 		>> BP_ANADIG_TEMPSENSE0_TEMP_VALUE;
-	writel(BM_ANADIG_TEMPSENSE0_FINISHED, &anatop->tempsense0_clr);
+	writel(BM_ANADIG_TEMPSENSE0_FINISHED, &mxc_ccm->tempsense0_clr);
 
 	if (tmp <= raw_n40c)
 		temperature = REG_VALUE_TO_CEL(ratio, tmp);
 	else
 		temperature = TEMPERATURE_MIN;
 	/* power down anatop thermal sensor */
-	writel(BM_ANADIG_TEMPSENSE0_POWER_DOWN, &anatop->tempsense0_set);
-	writel(BM_ANADIG_ANA_MISC0_REFTOP_SELBIASOFF, &anatop->ana_misc0_clr);
+	writel(BM_ANADIG_TEMPSENSE0_POWER_DOWN, &mxc_ccm->tempsense0_set);
+	writel(BM_ANADIG_ANA_MISC0_REFTOP_SELBIASOFF, &mxc_ccm->ana_misc0_clr);
 
 	return temperature;
 }
@@ -441,7 +440,7 @@ void pcie_power_off(void)
 
 static void imx_set_vddpu_power_down(void)
 {
-	struct anatop_regs *anatop = (struct anatop_regs *)ANATOP_BASE_ADDR;
+	struct mxc_ccm_reg *ccm_regs = (struct mxc_ccm_reg *)CCM_BASE_ADDR;
 	u32 val;
 
 	/* need to power down xPU in GPC before turn off PU LDO */
@@ -455,7 +454,7 @@ static void imx_set_vddpu_power_down(void)
 
 	/* disable VDDPU */
 	val = 0x3e00;
-	writel(val, &anatop->reg_core_clr);
+	writel(val, &ccm_regs->reg_core_clr);
 }
 
 #ifndef CONFIG_MX6SL
@@ -736,7 +735,6 @@ enum boot_device get_boot_device(void)
 
 void s_init(void)
 {
-	struct anatop_regs *anatop = (struct anatop_regs *)ANATOP_BASE_ADDR;
 	struct mxc_ccm_reg *ccm = (struct mxc_ccm_reg *)CCM_BASE_ADDR;
 	int is_6sx = is_cpu_type(MXC_CPU_MX6SX);
 	u32 mask480;
@@ -774,10 +772,10 @@ void s_init(void)
 		(periph2 != 0x3) && (periph1 != 0x3))
 		mask528 |= ANATOP_PFD_CLKGATE_MASK(2);
 
-	writel(mask480, &anatop->pfd_480_set);
-	writel(mask528, &anatop->pfd_528_set);
-	writel(mask480, &anatop->pfd_480_clr);
-	writel(mask528, &anatop->pfd_528_clr);
+	writel(mask480, &ccm->analog_pfd_480_set);
+	writel(mask528, &ccm->analog_pfd_528_set);
+	writel(mask480, &ccm->analog_pfd_480_clr);
+	writel(mask528, &ccm->analog_pfd_528_clr);
 }
 
 #ifdef CONFIG_LDO_BYPASS_CHECK
@@ -874,13 +872,13 @@ void prep_anatop_bypass(void)
 
 int set_anatop_bypass(int wdog_reset_pin)
 {
-	struct anatop_regs *anatop = (struct anatop_regs *)ANATOP_BASE_ADDR;
+	struct mxc_ccm_reg *ccm_regs = (struct mxc_ccm_reg *)CCM_BASE_ADDR;
 	struct wdog_regs *wdog;
-	u32 reg = readl(&anatop->reg_core);
+	u32 reg = readl(&ccm_regs->reg_core);
 
 	/* bypass VDDARM/VDDSOC */
 	reg = reg | (0x1F << 18) | 0x1F;
-	writel(reg, &anatop->reg_core);
+	writel(reg, &ccm_regs->reg_core);
 
 	if (wdog_reset_pin == 2)
 		wdog = (struct wdog_regs *) WDOG2_BASE_ADDR;
@@ -1082,12 +1080,14 @@ void set_usboh3_clk(void)
 void set_usb_phy1_clk(void)
 {
 	/* make sure pll3 is enable here */
+	struct mxc_ccm_reg *ccm_regs = (struct mxc_ccm_reg *)CCM_BASE_ADDR;
+
 	writel((BM_ANADIG_USB1_CHRG_DETECT_EN_B |
 		BM_ANADIG_USB1_CHRG_DETECT_CHK_CHRG_B),
-		ANATOP_BASE_ADDR + HW_ANADIG_USB1_CHRG_DETECT_SET);
+		&ccm_regs->usb1_chrg_detect_set);
 
 	writel(BM_ANADIG_USB1_PLL_480_CTRL_EN_USB_CLKS,
-		ANATOP_BASE_ADDR + HW_ANADIG_USB1_PLL_480_CTRL_SET);
+		&ccm_regs->analog_usb1_pll_480_ctrl_set);
 }
 void enable_usb_phy1_clk(unsigned char enable)
 {
diff --git a/arch/arm/include/asm/arch-mx6/crm_regs.h b/arch/arm/include/asm/arch-mx6/crm_regs.h
index 57842d7..7ac2015 100644
--- a/arch/arm/include/asm/arch-mx6/crm_regs.h
+++ b/arch/arm/include/asm/arch-mx6/crm_regs.h
@@ -64,8 +64,11 @@ struct mxc_ccm_reg {
 	u32 analog_usb1_pll_480_ctrl_set;
 	u32 analog_usb1_pll_480_ctrl_clr;
 	u32 analog_usb1_pll_480_ctrl_tog;
-	u32 analog_reserved0[4];
-	u32 analog_pll_528;			/* 0x4030 */
+	u32 analog_usb2_pll_480_ctrl;	/* 0x4020 */
+	u32 analog_usb2_pll_480_ctrl_set;
+	u32 analog_usb2_pll_480_ctrl_clr;
+	u32 analog_usb2_pll_480_ctrl_tog;
+	u32 analog_pll_528;			    /* 0x4030 */
 	u32 analog_pll_528_set;
 	u32 analog_pll_528_clr;
 	u32 analog_pll_528_tog;
@@ -90,7 +93,11 @@ struct mxc_ccm_reg {
 	u32 analog_pll_video_num;		/* 0x40b0 */
 	u32 analog_reserved6[3];
 	u32 analog_pll_video_denon;		/* 0x40c0 */
-	u32 analog_reserved7[7];
+	u32 analog_reserved7[3];
+	u32 analog_pll_mlb;		        /* 0x40d0 */
+	u32 analog_pll_mlb_set;
+	u32 analog_pll_mlb_clr;
+	u32 analog_pll_mlb_tog;
 	u32 analog_pll_enet;			/* 0x40e0 */
 	u32 analog_pll_enet_set;
 	u32 analog_pll_enet_clr;
@@ -103,6 +110,93 @@ struct mxc_ccm_reg {
 	u32 analog_pfd_528_set;
 	u32 analog_pfd_528_clr;
 	u32 analog_pfd_528_tog;
+	u32 reg_1p1;		/* 0x4110 */
+	u32 reg_1p1_set;		/* 0x4114 */
+	u32 reg_1p1_clr;		/* 0x4118 */
+	u32 reg_1p1_tog;		/* 0x411c */
+	u32 reg_3p0;		/* 0x4120 */
+	u32 reg_3p0_set;		/* 0x4124 */
+	u32 reg_3p0_clr;		/* 0x4128 */
+	u32 reg_3p0_tog;		/* 0x412c */
+	u32 reg_2p5;		/* 0x4130 */
+	u32 reg_2p5_set;		/* 0x4134 */
+	u32 reg_2p5_clr;		/* 0x4138 */
+	u32 reg_2p5_tog;		/* 0x413c */
+	u32 reg_core;		/* 0x4140 */
+	u32 reg_core_set;		/* 0x4144 */
+	u32 reg_core_clr;		/* 0x4148 */
+	u32 reg_core_tog;		/* 0x414c */
+	u32 ana_misc0;		/* 0x4150 */
+	u32 ana_misc0_set;		/* 0x4154 */
+	u32 ana_misc0_clr;		/* 0x4158 */
+	u32 ana_misc0_tog;		/* 0x415c */
+	u32 ana_misc1;		/* 0x4160 */
+	u32 ana_misc1_set;		/* 0x4164 */
+	u32 ana_misc1_clr;		/* 0x4168 */
+	u32 ana_misc1_tog;		/* 0x416c */
+	u32 ana_misc2;		/* 0x4170 */
+	u32 ana_misc2_set;		/* 0x4174 */
+	u32 ana_misc2_clr;		/* 0x4178 */
+	u32 ana_misc2_tog;		/* 0x417c */
+	u32 tempsense0;		/* 0x4180 */
+	u32 tempsense0_set;		/* 0x4184 */
+	u32 tempsense0_clr;		/* 0x4188 */
+	u32 tempsense0_tog;		/* 0x418c */
+	u32 tempsense1;		/* 0x4190 */
+	u32 tempsense1_set;		/* 0x4194 */
+	u32 tempsense1_clr;		/* 0x4198 */
+	u32 tempsense1_tog;		/* 0x419c */
+	u32 usb1_vbus_detect;	/* 0x41a0 */
+	u32 usb1_vbus_detect_set;	/* 0x41a4 */
+	u32 usb1_vbus_detect_clr;	/* 0x41a8 */
+	u32 usb1_vbus_detect_tog;	/* 0x41ac */
+	u32 usb1_chrg_detect;	/* 0x41b0 */
+	u32 usb1_chrg_detect_set;	/* 0x41b4 */
+	u32 usb1_chrg_detect_clr;	/* 0x41b8 */
+	u32 usb1_chrg_detect_tog;	/* 0x41bc */
+	u32 usb1_vbus_det_stat;	/* 0x41c0 */
+	u32 usb1_vbus_det_stat_set;	/* 0x41c4 */
+	u32 usb1_vbus_det_stat_clr;	/* 0x41c8 */
+	u32 usb1_vbus_det_stat_tog;	/* 0x41cc */
+	u32 usb1_chrg_det_stat;	/* 0x41d0 */
+	u32 usb1_chrg_det_stat_set;	/* 0x41d4 */
+	u32 usb1_chrg_det_stat_clr;	/* 0x41d8 */
+	u32 usb1_chrg_det_stat_tog;	/* 0x41dc */
+	u32 usb1_loopback;		/* 0x41e0 */
+	u32 usb1_loopback_set;	/* 0x41e4 */
+	u32 usb1_loopback_clr;	/* 0x41e8 */
+	u32 usb1_loopback_tog;	/* 0x41ec */
+	u32 usb1_misc;		/* 0x41f0 */
+	u32 usb1_misc_set;		/* 0x41f4 */
+	u32 usb1_misc_clr;		/* 0x41f8 */
+	u32 usb1_misc_tog;		/* 0x41fc */
+	u32 usb2_vbus_detect;	/* 0x4200 */
+	u32 usb2_vbus_detect_set;	/* 0x4204 */
+	u32 usb2_vbus_detect_clr;	/* 0x4208 */
+	u32 usb2_vbus_detect_tog;	/* 0x420c */
+	u32 usb2_chrg_detect;	/* 0x4210 */
+	u32 usb2_chrg_detect_set;	/* 0x4214 */
+	u32 usb2_chrg_detect_clr;	/* 0x4218 */
+	u32 usb2_chrg_detect_tog;	/* 0x421c */
+	u32 usb2_vbus_det_stat;	/* 0x4220 */
+	u32 usb2_vbus_det_stat_set;	/* 0x4224 */
+	u32 usb2_vbus_det_stat_clr;	/* 0x4228 */
+	u32 usb2_vbus_det_stat_tog;	/* 0x422c */
+	u32 usb2_chrg_det_stat;	/* 0x4230 */
+	u32 usb2_chrg_det_stat_set;	/* 0x4234 */
+	u32 usb2_chrg_det_stat_clr;	/* 0x4238 */
+	u32 usb2_chrg_det_stat_tog;	/* 0x423c */
+	u32 usb2_loopback;		/* 0x4240 */
+	u32 usb2_loopback_set;	/* 0x4244 */
+	u32 usb2_loopback_clr;	/* 0x4248 */
+	u32 usb2_loopback_tog;	/* 0x424c */
+	u32 usb2_misc;		/* 0x4250 */
+	u32 usb2_misc_set;		/* 0x4254 */
+	u32 usb2_misc_clr;		/* 0x4258 */
+	u32 usb2_misc_tog;		/* 0x425c */
+	u32 digprog;		/* 0x4260 */
+	u32 reserved1[7];
+	u32 digprog_sololite;	/* 0x4280 */
 };
 #endif
 
diff --git a/arch/arm/include/asm/arch-mx6/imx-regs.h b/arch/arm/include/asm/arch-mx6/imx-regs.h
index fad04f6..ed520ec 100644
--- a/arch/arm/include/asm/arch-mx6/imx-regs.h
+++ b/arch/arm/include/asm/arch-mx6/imx-regs.h
@@ -647,150 +647,6 @@ struct aipstz_regs {
 	u32	opacr4;
 };
 
-struct anatop_regs {
-	u32	pll_sys;		/* 0x000 */
-	u32	pll_sys_set;		/* 0x004 */
-	u32	pll_sys_clr;		/* 0x008 */
-	u32	pll_sys_tog;		/* 0x00c */
-	u32	usb1_pll_480_ctrl;	/* 0x010 */
-	u32	usb1_pll_480_ctrl_set;	/* 0x014 */
-	u32	usb1_pll_480_ctrl_clr;	/* 0x018 */
-	u32	usb1_pll_480_ctrl_tog;	/* 0x01c */
-	u32	usb2_pll_480_ctrl;	/* 0x020 */
-	u32	usb2_pll_480_ctrl_set;	/* 0x024 */
-	u32	usb2_pll_480_ctrl_clr;	/* 0x028 */
-	u32	usb2_pll_480_ctrl_tog;	/* 0x02c */
-	u32	pll_528;		/* 0x030 */
-	u32	pll_528_set;		/* 0x034 */
-	u32	pll_528_clr;		/* 0x038 */
-	u32	pll_528_tog;		/* 0x03c */
-	u32	pll_528_ss;		/* 0x040 */
-	u32	rsvd0[3];
-	u32	pll_528_num;		/* 0x050 */
-	u32	rsvd1[3];
-	u32	pll_528_denom;		/* 0x060 */
-	u32	rsvd2[3];
-	u32	pll_audio;		/* 0x070 */
-	u32	pll_audio_set;		/* 0x074 */
-	u32	pll_audio_clr;		/* 0x078 */
-	u32	pll_audio_tog;		/* 0x07c */
-	u32	pll_audio_num;		/* 0x080 */
-	u32	rsvd3[3];
-	u32	pll_audio_denom;	/* 0x090 */
-	u32	rsvd4[3];
-	u32	pll_video;		/* 0x0a0 */
-	u32	pll_video_set;		/* 0x0a4 */
-	u32	pll_video_clr;		/* 0x0a8 */
-	u32	pll_video_tog;		/* 0x0ac */
-	u32	pll_video_num;		/* 0x0b0 */
-	u32	rsvd5[3];
-	u32	pll_video_denom;	/* 0x0c0 */
-	u32	rsvd6[3];
-	u32	pll_mlb;		/* 0x0d0 */
-	u32	pll_mlb_set;		/* 0x0d4 */
-	u32	pll_mlb_clr;		/* 0x0d8 */
-	u32	pll_mlb_tog;		/* 0x0dc */
-	u32	pll_enet;		/* 0x0e0 */
-	u32	pll_enet_set;		/* 0x0e4 */
-	u32	pll_enet_clr;		/* 0x0e8 */
-	u32	pll_enet_tog;		/* 0x0ec */
-	u32	pfd_480;		/* 0x0f0 */
-	u32	pfd_480_set;		/* 0x0f4 */
-	u32	pfd_480_clr;		/* 0x0f8 */
-	u32	pfd_480_tog;		/* 0x0fc */
-	u32	pfd_528;		/* 0x100 */
-	u32	pfd_528_set;		/* 0x104 */
-	u32	pfd_528_clr;		/* 0x108 */
-	u32	pfd_528_tog;		/* 0x10c */
-	u32	reg_1p1;		/* 0x110 */
-	u32	reg_1p1_set;		/* 0x114 */
-	u32	reg_1p1_clr;		/* 0x118 */
-	u32	reg_1p1_tog;		/* 0x11c */
-	u32	reg_3p0;		/* 0x120 */
-	u32	reg_3p0_set;		/* 0x124 */
-	u32	reg_3p0_clr;		/* 0x128 */
-	u32	reg_3p0_tog;		/* 0x12c */
-	u32	reg_2p5;		/* 0x130 */
-	u32	reg_2p5_set;		/* 0x134 */
-	u32	reg_2p5_clr;		/* 0x138 */
-	u32	reg_2p5_tog;		/* 0x13c */
-	u32	reg_core;		/* 0x140 */
-	u32	reg_core_set;		/* 0x144 */
-	u32	reg_core_clr;		/* 0x148 */
-	u32	reg_core_tog;		/* 0x14c */
-	u32	ana_misc0;		/* 0x150 */
-	u32	ana_misc0_set;		/* 0x154 */
-	u32	ana_misc0_clr;		/* 0x158 */
-	u32	ana_misc0_tog;		/* 0x15c */
-	u32	ana_misc1;		/* 0x160 */
-	u32	ana_misc1_set;		/* 0x164 */
-	u32	ana_misc1_clr;		/* 0x168 */
-	u32	ana_misc1_tog;		/* 0x16c */
-	u32	ana_misc2;		/* 0x170 */
-	u32	ana_misc2_set;		/* 0x174 */
-	u32	ana_misc2_clr;		/* 0x178 */
-	u32	ana_misc2_tog;		/* 0x17c */
-	u32	tempsense0;		/* 0x180 */
-	u32	tempsense0_set;		/* 0x184 */
-	u32	tempsense0_clr;		/* 0x188 */
-	u32	tempsense0_tog;		/* 0x18c */
-	u32	tempsense1;		/* 0x190 */
-	u32	tempsense1_set;		/* 0x194 */
-	u32	tempsense1_clr;		/* 0x198 */
-	u32	tempsense1_tog;		/* 0x19c */
-	u32	usb1_vbus_detect;	/* 0x1a0 */
-	u32	usb1_vbus_detect_set;	/* 0x1a4 */
-	u32	usb1_vbus_detect_clr;	/* 0x1a8 */
-	u32	usb1_vbus_detect_tog;	/* 0x1ac */
-	u32	usb1_chrg_detect;	/* 0x1b0 */
-	u32	usb1_chrg_detect_set;	/* 0x1b4 */
-	u32	usb1_chrg_detect_clr;	/* 0x1b8 */
-	u32	usb1_chrg_detect_tog;	/* 0x1bc */
-	u32	usb1_vbus_det_stat;	/* 0x1c0 */
-	u32	usb1_vbus_det_stat_set;	/* 0x1c4 */
-	u32	usb1_vbus_det_stat_clr;	/* 0x1c8 */
-	u32	usb1_vbus_det_stat_tog;	/* 0x1cc */
-	u32	usb1_chrg_det_stat;	/* 0x1d0 */
-	u32	usb1_chrg_det_stat_set;	/* 0x1d4 */
-	u32	usb1_chrg_det_stat_clr;	/* 0x1d8 */
-	u32	usb1_chrg_det_stat_tog;	/* 0x1dc */
-	u32	usb1_loopback;		/* 0x1e0 */
-	u32	usb1_loopback_set;	/* 0x1e4 */
-	u32	usb1_loopback_clr;	/* 0x1e8 */
-	u32	usb1_loopback_tog;	/* 0x1ec */
-	u32	usb1_misc;		/* 0x1f0 */
-	u32	usb1_misc_set;		/* 0x1f4 */
-	u32	usb1_misc_clr;		/* 0x1f8 */
-	u32	usb1_misc_tog;		/* 0x1fc */
-	u32	usb2_vbus_detect;	/* 0x200 */
-	u32	usb2_vbus_detect_set;	/* 0x204 */
-	u32	usb2_vbus_detect_clr;	/* 0x208 */
-	u32	usb2_vbus_detect_tog;	/* 0x20c */
-	u32	usb2_chrg_detect;	/* 0x210 */
-	u32	usb2_chrg_detect_set;	/* 0x214 */
-	u32	usb2_chrg_detect_clr;	/* 0x218 */
-	u32	usb2_chrg_detect_tog;	/* 0x21c */
-	u32	usb2_vbus_det_stat;	/* 0x220 */
-	u32	usb2_vbus_det_stat_set;	/* 0x224 */
-	u32	usb2_vbus_det_stat_clr;	/* 0x228 */
-	u32	usb2_vbus_det_stat_tog;	/* 0x22c */
-	u32	usb2_chrg_det_stat;	/* 0x230 */
-	u32	usb2_chrg_det_stat_set;	/* 0x234 */
-	u32	usb2_chrg_det_stat_clr;	/* 0x238 */
-	u32	usb2_chrg_det_stat_tog;	/* 0x23c */
-	u32	usb2_loopback;		/* 0x240 */
-	u32	usb2_loopback_set;	/* 0x244 */
-	u32	usb2_loopback_clr;	/* 0x248 */
-	u32	usb2_loopback_tog;	/* 0x24c */
-	u32	usb2_misc;		/* 0x250 */
-	u32	usb2_misc_set;		/* 0x254 */
-	u32	usb2_misc_clr;		/* 0x258 */
-	u32	usb2_misc_tog;		/* 0x25c */
-	u32	digprog;		/* 0x260 */
-	u32	reserved1[7];
-	u32	digprog_sololite;	/* 0x280 */
-};
-
 #define ANATOP_PFD_FRAC_SHIFT(n)	((n)*8)
 #define ANATOP_PFD_FRAC_MASK(n)	(0x3f<<ANATOP_PFD_FRAC_SHIFT(n))
 #define ANATOP_PFD_STABLE_SHIFT(n)	(6+((n)*8))
diff --git a/board/freescale/mx6sabresd/mx6sabresd.c b/board/freescale/mx6sabresd/mx6sabresd.c
index c65b983..d24eea1 100644
--- a/board/freescale/mx6sabresd/mx6sabresd.c
+++ b/board/freescale/mx6sabresd/mx6sabresd.c
@@ -831,10 +831,10 @@ static void setup_epdc(void)
 	writel(reg, &ccm_regs->cscdr2);
 
 	/* PLL5 enable (defaults to 650) */
-	reg = readl(ANATOP_BASE_ADDR + ANATOP_PLL_VIDEO);
+	reg = readl(&ccm_regs->analog_pll_video);
 	reg &= ~((1 << 16) | (1 << 12));
 	reg |= (1 << 13);
-	writel(reg, ANATOP_BASE_ADDR + ANATOP_PLL_VIDEO);
+	writel(reg, &ccm_regs->analog_pll_video);
 
 	/* EPDC PIX clk enable */
 	reg = readl(&ccm_regs->CCGR3);
diff --git a/drivers/pci/pcie_imx.c b/drivers/pci/pcie_imx.c
index 0b5b886..9f3e604 100644
--- a/drivers/pci/pcie_imx.c
+++ b/drivers/pci/pcie_imx.c
@@ -103,6 +103,7 @@ static void print_regs(int contain_pcie_reg)
 #else
 	struct iomuxc *iomuxc_regs = (struct iomuxc *)IOMUXC_GPR_BASE_ADDR;
 #endif
+	struct mxc_ccm_reg *ccm_regs = (struct mxc_ccm_reg *)CCM_BASE_ADDR;
 	val = readl(&iomuxc_regs->gpr[1]);
 	DBGF("GPR01 a:0x%08x v:0x%08x\n", (u32)&iomuxc_regs->gpr[1], val);
 	val = readl(&iomuxc_regs->gpr[5]);
@@ -111,10 +112,10 @@ static void print_regs(int contain_pcie_reg)
 	DBGF("GPR08 a:0x%08x v:0x%08x\n", (u32)&iomuxc_regs->gpr[8], val);
 	val = readl(&iomuxc_regs->gpr[12]);
 	DBGF("GPR12 a:0x%08x v:0x%08x\n", (u32)&iomuxc_regs->gpr[12], val);
-	val = readl(ANATOP_BASE_ADDR + 0xe0);
-	DBGF("PLL06 a:0x%08x v:0x%08x\n", ANATOP_BASE_ADDR + 0xe0, val);
-	val = readl(ANATOP_BASE_ADDR + 0x160);
-	DBGF("MISC1 a:0x%08x v:0x%08x\n", ANATOP_BASE_ADDR + 0x160, val);
+	val = readl(&ccm_regs->analog_pll_enet);
+	DBGF("PLL06 a:0x%08x v:0x%08x\n", (u32)&ccm_regs->analog_pll_enet, val);
+	val = readl(&ccm_regs->ana_misc1);
+	DBGF("MISC1 a:0x%08x v:0x%08x\n", (u32)&ccm_regs->ana_misc1, val);
 	if (contain_pcie_reg) {
 		val = readl(MX6_DBI_ADDR + 0x728);
 		DBGF("dbr0 offset 0x728 %08x\n", val);
diff --git a/drivers/usb/host/ehci-mx6.c b/drivers/usb/host/ehci-mx6.c
index a316d92..005cf36 100644
--- a/drivers/usb/host/ehci-mx6.c
+++ b/drivers/usb/host/ehci-mx6.c
@@ -11,7 +11,7 @@
 #include <linux/compiler.h>
 #include <usb/ehci-fsl.h>
 #include <asm/io.h>
-#include <asm/arch/imx-regs.h>
+#include <asm/arch/crm_regs.h>
 #include <asm/arch/clock.h>
 #include <asm/imx-common/iomux-v3.h>
 
@@ -72,22 +72,22 @@ static void usb_internal_phy_clock_gate(int index, int on)
 
 static void usb_power_config(int index)
 {
-	struct anatop_regs __iomem *anatop =
-		(struct anatop_regs __iomem *)ANATOP_BASE_ADDR;
+	struct mxc_ccm_reg __iomem *ccm_regs =
+		(struct mxc_ccm_reg __iomem *)CCM_BASE_ADDR;
 	void __iomem *chrg_detect;
 	void __iomem *pll_480_ctrl_clr;
 	void __iomem *pll_480_ctrl_set;
 
 	switch (index) {
 	case 0:
-		chrg_detect = &anatop->usb1_chrg_detect;
-		pll_480_ctrl_clr = &anatop->usb1_pll_480_ctrl_clr;
-		pll_480_ctrl_set = &anatop->usb1_pll_480_ctrl_set;
+		chrg_detect = &ccm_regs->usb1_chrg_detect;
+		pll_480_ctrl_clr = &ccm_regs->analog_usb1_pll_480_ctrl_clr;
+		pll_480_ctrl_set = &ccm_regs->analog_usb1_pll_480_ctrl_set;
 		break;
 	case 1:
-		chrg_detect = &anatop->usb2_chrg_detect;
-		pll_480_ctrl_clr = &anatop->usb2_pll_480_ctrl_clr;
-		pll_480_ctrl_set = &anatop->usb2_pll_480_ctrl_set;
+		chrg_detect = &ccm_regs->usb2_chrg_detect;
+		pll_480_ctrl_clr = &ccm_regs->analog_usb2_pll_480_ctrl_clr;
+		pll_480_ctrl_set = &ccm_regs->analog_usb2_pll_480_ctrl_set;
 		break;
 	default:
 		return;