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| author | Ye.Li <B37916@freescale.com> | 2014-09-16 17:40:53 +0800 |
|---|---|---|
| committer | Ye.Li <B37916@freescale.com> | 2014-09-18 11:11:04 +0800 |
| commit | 1e468dfbe7c5ae117482d1dccaff94b8652f32aa (patch) | |
| tree | 1d83cdc0898decc677203a707799fd7e7bfdb6d0 | |
| parent | 1c6f3b6ec717bdf7e6a26996e399e050f66abcce (diff) | |
| download | u-boot-imx-1e468dfbe7c5ae117482d1dccaff94b8652f32aa.zip u-boot-imx-1e468dfbe7c5ae117482d1dccaff94b8652f32aa.tar.gz u-boot-imx-1e468dfbe7c5ae117482d1dccaff94b8652f32aa.tar.bz2 | |
ENGR00331706-4 imx: mx6sl: Set the preclk clock source to OSC 24Mhz
For MX6SL, uses the OSC 24Mhz as the preclk source in CCM. Align the
preclk setting with kernel.
Signed-off-by: Ye.Li <B37916@freescale.com>
| -rw-r--r-- | arch/arm/cpu/armv7/mx6/soc.c | 16 |
1 files changed, 16 insertions, 0 deletions
diff --git a/arch/arm/cpu/armv7/mx6/soc.c b/arch/arm/cpu/armv7/mx6/soc.c index 8b6b7c1..f1d2cea 100644 --- a/arch/arm/cpu/armv7/mx6/soc.c +++ b/arch/arm/cpu/armv7/mx6/soc.c @@ -393,6 +393,17 @@ static void init_bandgap(void) writel(BM_ANADIG_ANA_MISC0_REFTOP_SELBIASOFF, &mxc_ccm->ana_misc0_set); } +#ifdef CONFIG_MX6SL +static void set_preclk_from_osc(void) +{ + struct mxc_ccm_reg *mxc_ccm = (struct mxc_ccm_reg *)CCM_BASE_ADDR; + u32 reg; + + reg = readl(&mxc_ccm->cscmr1); + reg |= MXC_CCM_CSCMR1_PER_CLK_SEL_MASK; + writel(reg, &mxc_ccm->cscmr1); +} +#endif #ifdef CONFIG_MX6SX void vadc_power_up(void) @@ -537,6 +548,11 @@ int arch_cpu_init(void) if (mxc_get_clock(MXC_ARM_CLK) == 396000000) set_ahb_rate(132000000); + /* Set perclk to source from OSC 24MHz */ +#if defined(CONFIG_MX6SL) + set_preclk_from_osc(); +#endif + imx_set_wdog_powerdown(false); /* Disable PDE bit of WMCR register */ #ifndef CONFIG_MX6SL |