diff options
| author | Nitin Garg <nitin.garg@freescale.com> | 2014-09-02 17:33:06 -0500 |
|---|---|---|
| committer | Nitin Garg <nitin.garg@freescale.com> | 2014-09-04 10:37:37 -0500 |
| commit | 69f56f7509a4116fa0f2b9be50db256f1e628d31 (patch) | |
| tree | 9a1cac64f6629fd88d7b96e69bf3edc24eaac129 | |
| parent | ac62726276687242ce08ebe90ee765efb41abf3b (diff) | |
| download | u-boot-imx-69f56f7509a4116fa0f2b9be50db256f1e628d31.zip u-boot-imx-69f56f7509a4116fa0f2b9be50db256f1e628d31.tar.gz u-boot-imx-69f56f7509a4116fa0f2b9be50db256f1e628d31.tar.bz2 | |
ENGR00328278-1: Fix i.MX6DQ/DL arm2 LPDDR2 boards mem size
Couple of issues in commit 21a2eb5f. The RAM size is wrong and
max number of DCD is 220.
Signed-off-by: Nitin Garg <nitin.garg@freescale.com>
| -rw-r--r-- | board/freescale/mx6qarm2/mx6qarm2.c | 7 | ||||
| -rw-r--r-- | boards.cfg | 8 | ||||
| -rw-r--r-- | include/configs/mx6qarm2.h | 5 | ||||
| -rw-r--r-- | tools/imximage.h | 2 |
4 files changed, 11 insertions, 11 deletions
diff --git a/board/freescale/mx6qarm2/mx6qarm2.c b/board/freescale/mx6qarm2/mx6qarm2.c index 6f8c9b2..e1294bf 100644 --- a/board/freescale/mx6qarm2/mx6qarm2.c +++ b/board/freescale/mx6qarm2/mx6qarm2.c @@ -32,7 +32,12 @@ DECLARE_GLOBAL_DATA_PTR; int dram_init(void) { - gd->ram_size = get_ram_size((void *)PHYS_SDRAM, PHYS_SDRAM_SIZE); +#if defined(CONFIG_MX6DL) && !defined(CONFIG_MX6DL_LPDDR2) && \ + defined(CONFIG_DDR_32BIT) + gd->ram_size = ((ulong)CONFIG_DDR_MB * 1024 * 1024)/2; +#else + gd->ram_size = ((ulong)CONFIG_DDR_MB * 1024 * 1024); +#endif return 0; } @@ -317,10 +317,10 @@ Active arm armv7 mx6 boundary nitrogen6x Active arm armv7 mx6 boundary nitrogen6x nitrogen6s nitrogen6x:IMX_CONFIG=board/boundary/nitrogen6x/nitrogen6s.cfg,MX6S,DDR_MB=512 Eric Nelson <eric.nelson@boundarydevices.com> Active arm armv7 mx6 boundary nitrogen6x nitrogen6s1g nitrogen6x:IMX_CONFIG=board/boundary/nitrogen6x/nitrogen6s1g.cfg,MX6S,DDR_MB=1024 Eric Nelson <eric.nelson@boundarydevices.com> Active arm armv7 mx6 congatec cgtqmx6eval cgtqmx6qeval cgtqmx6eval:IMX_CONFIG=board/freescale/imx/ddr/mx6q_4x_mt41j128.cfg,MX6Q Leo Sartre <lsartre@adeneo-embedded.com> -Active arm armv7 mx6 freescale mx6qarm2 mx6qarm2 mx6qarm2:IMX_CONFIG=board/freescale/mx6qarm2/imximage.cfg,MX6Q,DDR_MB=1024 Jason Liu <r64343@freescale.com> -Active arm armv7 mx6 freescale mx6qarm2 mx6qarm2_lpddr2 mx6qarm2:IMX_CONFIG=board/freescale/mx6qarm2/imximage.cfg,MX6Q,MX6DQ_LPDDR2,DDR_MB=256 Jason Liu <r64343@freescale.com> -Active arm armv7 mx6 freescale mx6qarm2 mx6dlarm2 mx6qarm2:IMX_CONFIG=board/freescale/mx6qarm2/imximage_mx6dl.cfg,MX6DL,DDR_MB=1024 Jason Liu <r64343@freescale.com> -Active arm armv7 mx6 freescale mx6qarm2 mx6dlarm2_lpddr2 mx6qarm2:IMX_CONFIG=board/freescale/mx6qarm2/imximage_mx6dl.cfg,MX6DL,MX6DL_LPDDR2,DDR_MB=256 Jason Liu <r64343@freescale.com> +Active arm armv7 mx6 freescale mx6qarm2 mx6qarm2 mx6qarm2:IMX_CONFIG=board/freescale/mx6qarm2/imximage.cfg,MX6Q,DDR_MB=2048 Jason Liu <r64343@freescale.com> +Active arm armv7 mx6 freescale mx6qarm2 mx6qarm2_lpddr2 mx6qarm2:IMX_CONFIG=board/freescale/mx6qarm2/imximage.cfg,MX6Q,MX6DQ_LPDDR2,DDR_MB=512 Jason Liu <r64343@freescale.com> +Active arm armv7 mx6 freescale mx6qarm2 mx6dlarm2 mx6qarm2:IMX_CONFIG=board/freescale/mx6qarm2/imximage_mx6dl.cfg,MX6DL,DDR_MB=2048 Jason Liu <r64343@freescale.com> +Active arm armv7 mx6 freescale mx6qarm2 mx6dlarm2_lpddr2 mx6qarm2:IMX_CONFIG=board/freescale/mx6qarm2/imximage_mx6dl.cfg,MX6DL,MX6DL_LPDDR2,DDR_MB=512 Jason Liu <r64343@freescale.com> Active arm armv7 mx6 freescale mx6qsabreauto mx6qsabreauto mx6qsabreauto:IMX_CONFIG=board/freescale/mx6qsabreauto/mx6q.cfg,MX6Q,DEFAULT_FDT_FILE="imx6q-sabreauto.dtb",DDR_MB=2048 Fabio Estevam <fabio.estevam@freescale.com> Active arm armv7 mx6 freescale mx6qsabreauto mx6dlsabreauto mx6qsabreauto:IMX_CONFIG=board/freescale/mx6qsabreauto/mx6dl.cfg,MX6DL,DEFAULT_FDT_FILE="imx6dl-sabreauto.dtb",DDR_MB=2048 Fabio Estevam <fabio.estevam@freescale.com> Active arm armv7 mx6 freescale mx6qsabreauto mx6solosabreauto mx6qsabreauto:IMX_CONFIG=board/freescale/mx6qsabreauto/mx6solo.cfg,MX6SOLO,DEFAULT_FDT_FILE="imx6dl-sabreauto.dtb",DDR_MB=1024,SYS_NOSMP="nosmp" Fabio Estevam <fabio.estevam@freescale.com> diff --git a/include/configs/mx6qarm2.h b/include/configs/mx6qarm2.h index eea6293..70a7b89 100644 --- a/include/configs/mx6qarm2.h +++ b/include/configs/mx6qarm2.h @@ -185,11 +185,6 @@ /* Physical Memory Map */ #define CONFIG_NR_DRAM_BANKS 1 #define PHYS_SDRAM MMDC0_ARB_BASE_ADDR -#ifdef CONFIG_DDR_32BIT -#define PHYS_SDRAM_SIZE (1u * 1024 * 1024 * 1024) -#else -#define PHYS_SDRAM_SIZE (2u * 1024 * 1024 * 1024) -#endif #define CONFIG_SYS_SDRAM_BASE PHYS_SDRAM #define CONFIG_SYS_INIT_RAM_ADDR IRAM_BASE_ADDR diff --git a/tools/imximage.h b/tools/imximage.h index 0631c26..e97df0d 100644 --- a/tools/imximage.h +++ b/tools/imximage.h @@ -11,7 +11,7 @@ #define _IMXIMAGE_H_ #include <config.h> -#define MAX_HW_CFG_SIZE_V2 377 /* Max number of registers imx can set for v2 */ +#define MAX_HW_CFG_SIZE_V2 220 /* Max number of registers imx can set for v2 */ #define MAX_PLUGIN_CODE_SIZE (16*1024) #define MAX_HW_CFG_SIZE_V1 60 /* Max number of registers imx can set for v1 */ #define APP_CODE_BARKER 0xB1 |