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* MLK-9938 GIS: Enable GIS function on imx6sx SDB boardSandor Yu2014-12-02-1/+7
| | | | | | | | Enable GIS function on imx6sx SDB uboot. Expand CONFIG_SYS_MALLOC_LEN to 16M. Signed-off-by: Sandor Yu <R01008@freescale.com> (cherry picked from commit add90339c4e0ac9630f3c2a34d46b4f60265f56f)
* MLK-9933 imx:mx6sxsabresd correct info for PFUZEPeng Fan2014-11-30-1/+6
| | | | | | | | We use PFUZE200 for SX SDB RevB board and PFUZE100 for SX SDB RevA board. Show correct msg according DeviceID, since PFUZE200 and PFUZE100 have different DeviceID. PFUZE200's id is 1, while PFUZE100's is 0. Signed-off-by: Peng Fan <Peng.Fan@freescale.com>
* MLK-9927 - change the kernel and dtb location for nand readAllen Xu2014-11-30-6/+6
| | | | | | | | | kernel and dtb file location should be changed from 0x1000000 and 0x2000000 to 0x4000000 and 0x5000000, since the uboot partition expanded to 64M. Signed-off-by: Allen Xu <b45815@freescale.com> (cherry picked from commit eb4e6a6e65fe9074095869ecd5ccfe0a1559917d)
* MLK-9918: Reserve more space in uboot partition for NAND boot configurationsAllen Xu2014-11-22-7/+7
| | | | | | | | Expand the uboot space to 64m to reserve enough space for FCB, DBBT and u-boot. Signed-off-by: Allen Xu <b45815@freescale.com> (cherry picked from commit 54b3f6ba9097f4ed4cc8953a806c872444875a29)
* MLK-9898 imx:mx6 fix ana2 offset of fuse bank1Peng Fan2014-11-24-0/+2
| | | | | | | | | | According to RM, there is 16bytes between offset ana1 and offset ana2. So should add 3 int hole 'u32 reserved[3]' between ana1 and ana2. Also add the reserved bytes for ana2 in this patch. Signed-off-by: Peng Fan <Peng.Fan@freescale.com> (cherry picked from commit b0fd5f272895dfb0891872c099df7eef1519f729)
* MLK-9890 imx:mx6sxsabresd add bmode sd3 supportPeng Fan2014-11-21-0/+1
| | | | | | | | Current uboot does not support bmode sd3. So add this to make 'bmode sd3' command in uboot can work fine. Signed-off-by: Peng Fan <Peng.Fan@freescale.com> (cherry picked from commit 8f9c61e391687f9ef6e1f735040bd0d679320215)
* MLK-9854 mtd index change for imx6 sabreautoAllen Xu2014-11-16-0/+7
| | | | | | | | Modified the mtd index for imx6 sabreauto board, split the parallel nor to two partitions and the NAND index could be align with imx6sx board for mfgtool download. Signed-off-by: Allen Xu <b45815@freescale.com>
* MLK-9853 changed the mtd index for rootfs on imx6sx sabreautoAllen Xu2014-11-16-1/+1
| | | | | | | | On imx6sx sabreauto, both QSPI1 and NAND would be mapped as mtd devices, since we have already set the kernel to load QSPI1 first, the mtd index for NAND need to be changed. Signed-off-by: Allen Xu <b45815@freescale.com>
* MLK-9807: add 14x14 arm2 nand bootFrank Li2014-11-12-0/+1
| | | | | | Add 14x14 arm2 nand support Signed-off-by: Frank Li <Frank.Li@freescale.com>
* MLK-9819: ARM: mx6sx: clear WDOG3 Power Down Enable bit for i.mx6sxRobin Gong2014-11-11-0/+19
| | | | | | | | | | | Since we use WDOG_B reset now, we have to clear WDOG3 Power Down Enable bit to avoid system reboot during normal kernel boot. For mx6sxsabresd board, we have to make sure pad setting for WDOG_B ready before mux ready, otherwise also cause reboot. But that dependes on hardware design, only need on mx6sxsabresd board. Signed-off-by: Robin Gong <b38343@freescale.com> (cherry picked from commit 26875f93ac7e84748fa63e5f0dd948d12e663e43)
* MLK-9343 QSPI signal pin pad setting - drive strength too strongAllen Xu2014-11-10-8/+8
| | | | | | | | Changed the QSPI PAD setting, the previous output drive strength is too strong. Signed-off-by: Allen Xu <b45815@freescale.com> (cherry picked from commit 9dfb4a5ee01740eadb751ca5c9edfbec6f5059e3)
* MLK-9748 imx: mx6sxsabreauto: Add GIS supportYe.Li2014-11-06-1/+7
| | | | | | | | | | MX6SX sabreauto board has analog video input from VADC. Add the GIS support for this board that video input can display on LVDS at booting. The environment variable "gis" must be set to "vadc" to enable the function. Signed-off-by: Ye.Li <B37916@freescale.com> (cherry picked from commit 5f2008a6dc08f07d462a063a0642f5e54fedbd21)
* MLK-9733 imx: mx6sxsabreauto/mx6sxarm2: Fix nand clock glitchYe.Li2014-10-24-3/+18
| | | | | | | Since the qspi2_clk_root is the root clock of u_gpmi_bch_input_gpmi_io_clk, before switching the parent of qspi2_clk_root, we must gate off it. Signed-off-by: Ye.Li <B37916@freescale.com>
* MLK-9734 imx: mx6sxsabreauto: Add NAND boot environment variablesYe.Li2014-10-24-0/+23
| | | | | | | For NAND boot, the kernel zImage and rootfs also need to load from NAND. Add the environment variables for this. Signed-off-by: Ye.Li <B37916@freescale.com>
* MLK-9697 pcie: PERST_GPIO and POWER_GPIO are currently swappedRichard Zhu2014-10-24-2/+2
| | | | | | Fix the GPIO assignments as per the board schematics. Signed-off-by: Richard Zhu <richard.zhu@freescale.com>
* MLK-9735 new config for 19x19 ARM2 board NAND bootAllen Xu2014-10-23-0/+1
| | | | | | supported NAND boot on 19x19 ARM2 board. Signed-off-by: Allen Xu <b45815@freescale.com>
* MLK-9714 imx: imximage tool: Fixed the bootdata.size calculationYe.Li2014-10-22-1/+1
| | | | | | | | The bootdata.size should contain the IVT offset part, but the calculation for bootdata.size in imximage tool does not. This will cause some data at the end of image not be loaded into memory. Signed-off-by: Ye.Li <B37916@freescale.com>
* MLK-9706 imx: mx6sx19x19arm2: Fix ENET card MAX7322 reset issueYe.Li2014-10-20-5/+5
| | | | | | | | | | | The MAX7322 will fail to work on 19x19 arm2 revB board. This failure is caused by the MAX7322 reset pin is not released when calling the setup_fec function. The MAX7322 reset pin is same as PHY reset pin. This patch fixes the issue by moving the PHY reset from setup_iomux_fec1 to setup_fec. Signed-off-by: Ye.Li <B37916@freescale.com>
* MLK-9705 imx: mx6sxsabreauto: add MAX7310 support to reset peripheralsYe.Li2014-10-20-0/+46
| | | | | | | | | The MAX7310 uses I2C3 bus. At system initialization, enable the driver to: 1. Reset CPU_PER_RST_B signal 2. Set the steering for ENET 3. Enable the LVDS display Signed-off-by: Ye.Li <B37916@freescale.com>
* MLK-9705 imx: mx6sx: Set the pad setting SION for I2C3 pinsYe.Li2014-10-20-2/+2
| | | | | | When set the pinmux to I2C functionality, the SION is required to enabled. Signed-off-by: Ye.Li <B37916@freescale.com>
* MLK-9676 imx: mx6sx 19x19arm2: Fix ethernet phy reset issueYe.Li2014-10-11-2/+2
| | | | | | | The PHY reset on 19x19 arm2 board is GPIO6_18, not GPIO4_22. This causes the ethernet phy failed to work. Signed-off-by: Ye.Li <B37916@freescale.com>
* MLK-9652 Android: imx6sxsabreauto: Add android features supportYe.Li2014-10-09-0/+170
| | | | | | Add android fastboot, recovery and booti support for mx6sx sabreauto board. Signed-off-by: Ye.Li <B37916@freescale.com>
* MLK-9668 imx: mx6sxsabreauto: Fix bmode valueYe.Li2014-10-09-3/+3
| | | | | | Set the correct bmode value for booting from SDA/SDB/QSPI1/NAND Signed-off-by: Ye.Li <B37916@freescale.com>
* MLK-9665-2 mx6sx: define CONFIG_SPI_FLASH_BARPeng Fan2014-10-09-0/+3
| | | | | | | | | | | | define CONFIG_SPI_FLASH_BAR in mx6sx_arm2.h mx6sxsabreauto.h to enable access to flash array higher than 16MB. CONFIG_SPI_FLASH_BAR is also set in mx6sxsabresd.h for RevB board. Actually, if QSPI flash size <= 16MB, setting CONFIG_SPI_FLASH_BAR has not effect. Signed-off-by: Peng Fan <Peng.Fan@freescale.com>
* MLK-9665-1 QuadSPI: Support flash bigger than 16MBPeng Fan2014-10-09-1/+50
| | | | | | | | | | | | By introducing CONFIG_SPI_FLASH_BAR and add related command in LUT to enable fsl_qspi.c can handle flash size bigger that 16M. Because uboot does not support 32bits address access, this means bank address should be used to access bigger flash. It is hard to let qspi driver dynamically set LUT, so BRRD BRWR RDEAR and WREAR are all supported. Signed-off-by: Peng Fan <Peng.Fan@freescale.com>
* MLK-9636 QuadSPI: add 4k erase supportPeng Fan2014-10-08-1/+13
| | | | | | | | OPCODE_BE_4K is supported. To qspi flashes which support 4k sector erase, spi framework will use OPCODE_BE_4K command. Thus add this support to let uboot can erase such qspi flashes. Signed-off-by: Peng Fan <Peng.Fan@freescale.com>
* MLK-9640 ARM: imx6sx: enable ldo-bypass on mx6sxsabresd boardRobin Gong2014-09-30-16/+109
| | | | | | enable ldo-bypass check on all mx6sxsabresd boards. Signed-off-by: Robin Gong <b38343@freescale.com>
* MLK-9646 imx: mx6sxsabreauto: Change DDR size to 2GYe.Li2014-09-29-1/+1
| | | | | | | | The mx6sx sabreauto boards uses 2G DDR3. Modify the configuration PHYS_SDRAM_SIZE to this size. Signed-off-by: Ye.Li <B37916@freescale.com> Acked-by: Jason Liu
* ENGR00333317 imx: mx6sxsabreauto: Add BSP support for AI boardYe.Li2014-09-26-0/+1589
| | | | | | | | | | | | | | | | Create mx6sx sabreauto BSP file and configurations. The devices below have been supported: 1. SD/MMC/eMMC on SDA/SDB (base board) sockets 2. USB OTG port and USB HOST port (base board) 3. NAND flash 4. QuadSPI flash on QSPI1 5. I2C 6. PMIC PFUZE100 7. Onboard ethernet chip on ENET2 8. Splash screen on LVDS Signed-off-by: Ye.Li <B37916@freescale.com>
* ENGR00333299: Add support for i.MX6SX 14x14 lpddr2 arm2 boardNitin Garg2014-09-25-0/+302
| | | | | | | Add support for i.MX6SX 14x14 lpddr2 arm2 board, same as 17x17 arm2 except lpddr2 instead of ddr3. Signed-off-by: Nitin Garg <nitin.garg@freescale.com>
* sf: probe: Fix quad bit set pathPoddar, Sourav2014-09-25-10/+10
| | | | | | | | | | Currently, flash quad bit is set in "spi_flash_validate_params" and later at the end in the same api, we write 0 to status register for few flashes, thereby overriding the quad bit set. This fix moves the quad bit setting outside this api in "spi_flash_probe_slave" Signed-off-by: Sourav Poddar <sourav.poddar@ti.com> Reviewed-by: Jagannadha Sutradharudu Teki <jaganna@xilinx.com>
* ENGR00332535 imx: mx6sx: Remove WEIM plugin work around for TO 1.2 and higherYe.Li2014-09-23-1/+7
| | | | | | | | ROM fixes the WEIM plugin issue in TO 1.2. The work around for hacking WEIM base address to ROM variable is not needed. To avoid hacking useful data, remove the work around for TO 1.2 and higher revisions. Signed-off-by: Ye.Li <B37916@freescale.com>
* ENGR00331269 arm: mx6: select OSC as uart's clk parentAnson Huang2014-09-18-0/+9
| | | | | | | | As M4 is sourcing UART clk from OSC, to make UART work when M4 is enabled, need to select OSC as clk parent, 24M OSC is enough for debug UART in uboot. Signed-off-by: Anson Huang <b20788@freescale.com>
* ENGR00331706-5 imx: mx6: Enable 24Mhz OSC for GPTYe.Li2014-09-18-0/+1
| | | | | | | Set the CONFIG_MXC_GPT_HCLK configuration in mx6_common.h, so that enable the 24Mhz OSC GPT on all MX6 platforms. Signed-off-by: Ye.Li <B37916@freescale.com>
* ENGR00331706-4 imx: mx6sl: Set the preclk clock source to OSC 24MhzYe.Li2014-09-18-0/+16
| | | | | | | For MX6SL, uses the OSC 24Mhz as the preclk source in CCM. Align the preclk setting with kernel. Signed-off-by: Ye.Li <B37916@freescale.com>
* ENGR00331706-3 imx: mx6: Change the get_ipg_per_clk for OSC 24Mhz sourceYe.Li2014-09-18-0/+4
| | | | | | | For MX6SL and MX6SX, the perclk can come from OSC 24Mhz source. Fix the get_ipg_per_clk function to support it. Signed-off-by: Ye.Li <B37916@freescale.com>
* ENGR00331706-2 imx: mx6sl: Add perclk_clk_sel bit define in CCMYe.Li2014-09-18-0/+2
| | | | | | | The MX6SL has the perclk_clk_sel to select the perclk source. Add its define in CCM Signed-off-by: Ye.Li <B37916@freescale.com>
* ENGR00331706-1 imx: gpt: Add 24Mhz OSC clock source support for GPTYe.Li2014-09-18-10/+66
| | | | | | | | | | | | | | | | Introduce a new configuration "CONFIG_MXC_GPT_HCLK". When it is set, the GPT will use 24Mhz OSC as clock source. Otherwise, the GPT will use 32Khz OSC as clock source. Since only the GPT on iMX6 series provide the clock source option for 24Mhz OSC. For other series(MX5), if the configuration is set, the perclk will be selected as clock source. MX6Q/D Rev 1.0 and MX6SL can't use the 24Mhz OSC clock source option, so select the perclk for them. For MX6SL, we will set the OSC 24Mhz to perclk in CCM, so eventually the clock comes from OSC 24Mhz. Signed-off-by: Ye.Li <B37916@freescale.com>
* ENGR00327364 iMX6: Ensure that the bandgap self-bias circuit is disabled ↵Ranjani Vaidyanathan2014-09-10-0/+24
| | | | | | | | | | | | after boot. The self-bias circuit is used by the bandgap during startup. Once the bandgap has stabilized, the self-bias circuit should be disabled for best noise performance of analog blocks. Also this bit should be disabled before the chip enters STOP mode or when ever the regular bandgap is disabled. Signed-off-by: Ranjani Vaidyanathan <Ranjani.Vaidyanathan@freescale.com>
* ENGR00330792 imx: mx6: Merge anatop registers to CCM structureYe.Li2014-09-10-216/+160
| | | | | | | | | | THe anatop registers structure is duplicated with CCM structure at PLL fields. Since we are suggested not to use the name "anatop" any longer, merge the anatop registers to the CCM structure "mxc_ccm_reg" and use CCM to replace anatop. Signed-off-by: Ye.Li <B37916@freescale.com>
* ENGR00329484-2 ARM:MX6: Clear Align bit in SCTLRPeng Fan2014-09-05-0/+3
| | | | | | | | | | This problem is found when debugging QuadSPI. When "A" bit is enabled, unaligned access will cause data abort exception. Actually, we do not want this exception. So clear the align bit for MX6 SOCs. Tested this code with android team colleague and did not find problem. Signed-off-by: Peng Fan <Peng.Fan@freescale.com>
* ENGR00329484-1 QuadSPI:Unaligned access crash ubootPeng Fan2014-09-05-5/+25
| | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | To fsl_qspi_write_data and fsl_qspi_ip_read, pointer txbuf and rxbuf are not guaranteed that they are 4 Bytes aligned. Also, it it not a good idea to cast type 'u8 *' to 'u32 *', except we are sure that pointer type 'u8 *' is 4 Bytes aligned and cast it to 'u32 *' will not pass memory boundary. The problem is found when using fsl_qspi_write_data to write registers in flash devices. The err msg: data abort pc : [<87822f44>] lr : [<87822f38>] sp : bf5512c8 ip : 0000001c fp : bf856608 r10: 87868904 r9 : bf551efc r8 : 200f048c r7 : 00000002 r6 : bf551336 r5 : bf552a70 r4 : 00000001 r3 : 00000000 r2 : 00000060 r1 : 8783b520 r0 : 8783b520 Flags: nZCv IRQs on FIQs off Mode SVC_32 Resetting CPU ... The asm code which cause data abort is: 87822f30: e5964000 ldr r4, [r6] From the dump msg, r6 is not 4 Bytes aligned, and data abort exception. So, Use mempcy but not unsafe type casting. In this patch, max_write_size is assigned using txfifo to avoid possible errors in future. Signed-off-by: Peng Fan <Peng.Fan@freescale.com>
* ENGR00328278-1: Fix i.MX6DQ/DL arm2 LPDDR2 boards mem sizeNitin Garg2014-09-04-11/+11
| | | | | | | Couple of issues in commit 21a2eb5f. The RAM size is wrong and max number of DCD is 220. Signed-off-by: Nitin Garg <nitin.garg@freescale.com>
* ENGR00323255 Fixed QSPI randomly access timeout issueAllen Xu2014-08-29-16/+22
| | | | | | | | | | | | | | | | The QSPI clock rate was set without disabling the clock gate, the randomly glitch may mess up the clock and there will be no clock output, when kernel boot up the QSPI access will fail. To debug this issueon i.MX6SX SDB, changed the u-boot bootscript to 'sf probe; reset' to keep rebooting, the issue can be reproduced in 20 mins, set clock out register in CCM and measured TP86, found there is no clock ouput. To fix this bug, disable clock gate before changing clock rate. NOTICE: QSPI2 and GPMI_BCH_INPUT_GPMI_IO share the same clock gate, need to disable both of them. Signed-off-by: Allen Xu <b45815@freescale.com>
* ENGR00329631: imx6: fix kernel suspend reboot if keep watchdog aliveRobin Gong2014-09-02-0/+5
| | | | | | | WDZST bit is write-once only bit. So we need take care the setting in kernel ,otherwise, kernel setting will never be enabled. Signed-off-by: Robin Gong <b38343@freescale.com>
* ENGR00328278: Add support for i.MX6DQ/DL arm2 LPDDR2 boardsNitin Garg2014-08-28-8/+989
| | | | | | Add support for i.MX6DQ/DL arm2 LPDDR2 boards. Signed-off-by: Nitin Garg <nitin.garg@freescale.com>
* ENGR00326277-2 imx6: watchdog: use WDOG_B mode for wdog reset in ldo-bypass modeRobin Gong2014-08-26-7/+28
| | | | | | In ldo-bypass mode, we need trigger WDOG_B pin to reset pmic in ldo-bypass mode. Signed-off-by: Robin Gong <b38343@freescale.com>
* ENGR00326277-1: imx6: ldo_bypass: fix VDDARM voltage setting violate datasheetRobin Gong2014-08-26-11/+145
| | | | | | | | | Current only set VDDARM_IN@1.175V/VDDSOC_IN@1.175V before ldo bypass switch. So untile ldo bypass switch happened, these voltage setting is set in ldo-enable mode. But in datasheet, we need 1.15V + 125mV = 1.275V for VDDARM_IN. We need to downgrade cpufreq to 400Mhz and restore after ldo bypass mode switch. Signed-off-by: Robin Gong <b38343@freescale.com>
* ENGR00328312 i2c: imx: Optimize the i2c device recovery solutionFugang Duan2014-08-25-2/+25
| | | | | | | | | | | | | | | From i2c spec, if device pull down the SDA line that causes i2c bus dead, host can send out 9 clock to let device release SDA. But for some special device like pfuze100, it pull down SDA line and the solution cannot take effort. The patch just add NACK and STOP signal after 8 dummy clock, and pmic can release SDA line after the recovery. Test case catch 375 times of i2c hang, and all are recovered. Signed-off-by: Fugang Duan <B38611@freescale.com>
* ENGR00326994 iMX6: Checking PLL2 PFD0 and PFD2 for periph_clk before resetYe.Li2014-08-15-7/+16
| | | | | | | | | | | | | u-boot v2014 upstream codes have a problem in pfd reset (s_init function) that imx6 Dual is not applied for PLL2 PFD2 reset. It is originated by using dynamical cpu type checking and introducing two cpu types: MXC_CPU_MX6Q and MXC_CPU_MX6D for iMX6 Dual/Quad platform. Fixed this problem by checking the pre_periph_clk_sel and pre_periph2_clk of CCM CBCMR register, if the PLL2 PFD0 or PLL2 PFD2 is used for the clock source, do not reset this PFD to avoid system hang. Signed-off-by: Ye.Li <B37916@freescale.com>
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