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| * | sh: Add support Renesas SH7203 processorNobuhiro Iwamatsu2008-08-31-0/+41
| | | | | | | | | | | | | | | Signed-off-by: Nobuhiro Iwamatsu <iwamatsu.nobuhiro@renesas.com> Signed-off-by: Nobuhiro Iwamatsu <iwamatsu@nigauri.org>
| * | sh: Add support SH2/SH2A which is CPU of Renesas TechnologyNobuhiro Iwamatsu2008-08-31-1/+44
| | | | | | | | | | | | | | | | | | | | | Add support SH2/SH2A basic function. Signed-off-by: Nobuhiro Iwamatsu <iwamatsu.nobuhiro@renesas.com> Signed-off-by: Nobuhiro Iwamatsu <iwamatsu@nigauri.org>
| * | sh: Renesas R0P7785LC0011RL board supportNobuhiro Iwamatsu2008-08-31-0/+167
| | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | This board has SH7785, 512MB DDR2-SDRAM, NOR Flash, Graphic, Ethernet, USB, SD, RTC, and I2C controller. This patch supports the following functions: - 128MB DDR2-SDRAM (29-bit address mode only) - NOR Flash - USB host - Ethernet Signed-off-by: Yoshihiro Shimoda <shimoda.yoshihiro@renesas.com> Signed-off-by: Nobuhiro Iwamatsu <iwamatsu@nigauri.org>
| * | sh: add support for SH7785Yoshihiro Shimoda2008-08-31-0/+158
| |/ | | | | | | | | | | | | | | Renesas SH7785 has DDR2-SDRAM controller, PCI, and other. This patch supports CPU register's header file. Signed-off-by: Yoshihiro Shimoda <shimoda.yoshihiro@renesas.com> Signed-off-by: Nobuhiro Iwamatsu <iwamatsu@nigauri.org>
* | Merge branch 'master' of git://git.denx.de/u-boot-mpc5xxxWolfgang Denk2008-08-31-0/+95
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| * | Move MPC5xxx_FEC driver to drivers/netBen Warren2008-08-29-0/+93
| | | | | | | | | | | | Signed-off-by: Ben Warren <biggerbadderben@gmail.com>
| * | ADS5121: Fix NOR and CPLD ALE timing for rev 2 siliconJohn Rigby2008-08-28-0/+2
| |/ | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | MPC5121 rev 2 silicon has a new register for controlling how long CS is asserted after deassertion of ALE in multiplexed mode. The default is to assert CS together with ALE. The alternative is to assert CS (ALEN+1)*LPC_CLK clocks after deassertion of ALE. The default is wrong for the NOR flash and CPLD on the ADS5121. This patch turns on the alternative for CS0 (NOR) and CS2 (CPLD) it does so conditionally based on silicon rev 2.0 or greater. Signed-off-by: Martha J Marx <mmarx@silicontkx.com> Signed-off-by: John Rigby <jrigby@freescale.com>
* | ColdFire: I2C fix for multiple platformsTsiChung Liew2008-08-28-11/+19
| | | | | | | | Signed-off-by: TsiChung Liew <Tsi-Chung.Liew@freescale.com>
* | ColdFire: Add CONFIG_MII_INIT for M5272C3TsiChung Liew2008-08-28-0/+1
| | | | | | | | Signed-off-by: TsiChung Liew <Tsi-Chung.Liew@freescale.com>
* | ColdFire: Multiple fixes for MCF5445x platformsTsiChung Liew2008-08-28-7/+3
| | | | | | | | | | | | | | | | | | | | Add FEC pin set and mii reset in __mii_init(). Change legacy flash vendor from 2 to AMD LEGACY (0xFFF0), change cfi_offset to 0, and change CFG_FLASH_CFI to CONFIG_FLASH_CFI_LEGACY. Correct M54451EVB and M54455EVB env settings in configuration file. Signed-off-by: TsiChung Liew <Tsi-Chung.Liew@freescale.com>
* | ColdFire: Change the SDRAM BRD2WT timing from 3 to 7TsiChung Liew2008-08-28-2/+2
| | | | | | | | | | | | | | The user manuals recommend 7. Signed-off-by: Kurt Mahan <kmahan@freescale.com> Acked-by: TsiChung Liew <Tsi-Chung.Liew@freescale.com>
* | ColdFire: Raise uart baudrate to 115200 bpsTsiChung Liew2008-08-28-8/+8
|/ | | | | | | M5249EVB, M5271EVB, M5272C3, M5275EVB and M5282EVB platforms uart baudrate increase from 19200 to 115200 bps Signed-off-by: TsiChung Liew <Tsi-Chung.Liew@freescale.com>
* Merge branch 'master' of git://git.denx.de/u-boot-mpc5xxxWolfgang Denk2008-08-28-0/+376
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| * mpc52xx: added support for the MPC5200 based MUC.MC52 board from MAN.Heiko Schocher2008-08-27-0/+376
| | | | | | | | Signed-off-by: Heiko Schocher <hs@denx.de>
* | mpc85xx: Add support for the MPC8536DS reference boardKumar Gala2008-08-27-0/+594
| | | | | | | | | | | | | | | | | | Signed-off-by: Kumar Gala <galak@kernel.crashing.org> Signed-off-by: Srikanth Srinivasan <srikanth.srinivasan@freescale.com> Signed-off-by: Dejan Minic <minic@freescale.com> Signed-off-by: Jason Jin <Jason.jin@freescale.com> Signed-off-by: Dave Liu <daveliu@freescale.com> Signed-off-by: Kumar Gala <galak@kernel.crashing.org>
* | mpc85xx: Add support for the MPC8536Kumar Gala2008-08-27-3/+18
| | | | | | | | | | | | | | | | | | | | | | The MPC8536 Adds SDHC and SATA controllers to the PQ3 family. We also have SERDES init code for the 8536. Signed-off-by: Kumar Gala <galak@kernel.crashing.org> Signed-off-by: Srikanth Srinivasan <srikanth.srinivasan@freescale.com> Signed-off-by: Dejan Minic <minic@freescale.com> Signed-off-by: Jason Jin <Jason.jin@freescale.com> Signed-off-by: Dave Liu <daveliu@freescale.com>
* | mpc85xx: Add support for the MPC8572DS reference boardKumar Gala2008-08-27-0/+576
| | | | | | | | Signed-off-by: Kumar Gala <galak@kernel.crashing.org>
* | FSL DDR: Remove old SPD support from cpu/mpc85xxKumar Gala2008-08-27-0/+4
| | | | | | | | | | | | | | All 85xx boards have been converted to the new code so we can remove the old SPD DDR setup code. Signed-off-by: Kumar Gala <galak@kernel.crashing.org>
* | FSL DDR: Convert STXSSA to new DDR code.Kumar Gala2008-08-27-13/+17
| | | | | | | | Signed-off-by: Kumar Gala <galak@kernel.crashing.org>
* | FSL DDR: Convert STXGP3 to new DDR code.Kumar Gala2008-08-27-13/+17
| | | | | | | | Signed-off-by: Kumar Gala <galak@kernel.crashing.org>
* | FSL DDR: Convert SBC8560 to new DDR code.Kumar Gala2008-08-27-9/+41
| | | | | | | | Signed-off-by: Kumar Gala <galak@kernel.crashing.org>
* | FSL DDR: Convert MPC8540EVAL to new DDR code.Kumar Gala2008-08-27-7/+19
| | | | | | | | Signed-off-by: Kumar Gala <galak@kernel.crashing.org>
* | FSL DDR: Convert PM856 to new DDR code.Kumar Gala2008-08-27-30/+28
| | | | | | | | Signed-off-by: Kumar Gala <galak@kernel.crashing.org>
* | FSL DDR: Convert PM854 to new DDR code.Kumar Gala2008-08-27-30/+28
| | | | | | | | Signed-off-by: Kumar Gala <galak@kernel.crashing.org>
* | FSL DDR: Convert sbc8548 to new DDR code.Kumar Gala2008-08-27-13/+18
| | | | | | | | Signed-off-by: Kumar Gala <galak@kernel.crashing.org>
* | FSL DDR: Convert atum8548 to new DDR code.Kumar Gala2008-08-27-32/+30
| | | | | | | | Signed-off-by: Kumar Gala <galak@kernel.crashing.org>
* | FSL DDR: Convert socrates to new DDR code.Kumar Gala2008-08-27-11/+18
| | | | | | | | Signed-off-by: Kumar Gala <galak@kernel.crashing.org>
* | FSL DDR: Convert MPC8544DS to new DDR code.Kumar Gala2008-08-27-18/+20
| | | | | | | | Signed-off-by: Kumar Gala <galak@kernel.crashing.org>
* | FSL DDR: Convert MPC8568MDS to new DDR code.Jon Loeliger2008-08-27-18/+20
| | | | | | | | | | Signed-off-by: Jon Loeliger <jdl@freescale.com> Signed-off-by: Kumar Gala <galak@kernel.crashing.org>
* | FSL DDR: Convert MPC8548CDS to new DDR code.Jon Loeliger2008-08-27-17/+20
| | | | | | | | | | Signed-off-by: Jon Loeliger <jdl@freescale.com> Signed-off-by: Kumar Gala <galak@kernel.crashing.org>
* | FSL DDR: Convert MPC8541CDS to new DDR code.Jon Loeliger2008-08-27-13/+17
| | | | | | | | | | Signed-off-by: Jon Loeliger <jdl@freescale.com> Signed-off-by: Kumar Gala <galak@kernel.crashing.org>
* | FSL DDR: Convert MPC8555ADS to new DDR code.Jon Loeliger2008-08-27-17/+18
| | | | | | | | | | Signed-off-by: Jon Loeliger <jdl@freescale.com> Signed-off-by: Kumar Gala <galak@kernel.crashing.org>
* | FSL DDR: Convert MPC8560ADS to new DDR code.Jon Loeliger2008-08-27-28/+24
| | | | | | | | | | Signed-off-by: Jon Loeliger <jdl@freescale.com> Signed-off-by: Kumar Gala <galak@kernel.crashing.org>
* | FSL DDR: Convert MPC8540ADS to new DDR code.Kumar Gala2008-08-27-30/+23
| | | | | | | | Signed-off-by: Kumar Gala <galak@kernel.crashing.org>
* | FSL DDR: Add e500 TLB helper for DDR codeKumar Gala2008-08-27-0/+1
|/ | | | | | | Provide a helper function that board code can call to map TLBs when setting up DDR. Signed-off-by: Kumar Gala <galak@kernel.crashing.org>
* FSL DDR: Convert SBC8641D to new DDR code.Kumar Gala2008-08-27-2/+4
| | | | Signed-off-by: Kumar Gala <galak@kernel.crashing.org>
* FSL DDR: Convert MPC8610HPCD to new DDR code.Jon Loeliger2008-08-27-23/+20
| | | | | Signed-off-by: Jon Loeliger <jdl@freescale.com> Signed-off-by: Kumar Gala <galak@kernel.crashing.org>
* FSL DDR: Convert MPC8641HPCN to new DDR code.Kumar Gala2008-08-27-53/+50
| | | | | Signed-off-by: Jon Loeliger <jdl@freescale.com> Signed-off-by: Kumar Gala <galak@kernel.crashing.org>
* FSL DDR: Rewrite the FSL mpc8xxx DDR controller setup code.Kumar Gala2008-08-27-0/+137
| | | | | | | | | | | | | | | | | | | | | | | | | | | | The main purpose of this rewrite it to be able to share the same initialization code on all FSL PowerPC products that have DDR controllers. (83xx, 85xx, 86xx). The code is broken up into the following steps: GET_SPD COMPUTE_DIMM_PARMS COMPUTE_COMMON_PARMS GATHER_OPTS ASSIGN_ADDRESSES COMPUTE_REGS PROGRAM_REGS This allows us to share more code an easily allow for board specific code overrides. Additionally this code base adds support for >4G of DDR and provides a foundation for supporting interleaving on processors with more than one controller. Signed-off-by: James Yang <James.Yang@freescale.com> Signed-off-by: Jon Loeliger <jdl@freescale.com> Signed-off-by: Becky Bruce <becky.bruce@freescale.com> Signed-off-by: Ed Swarthout <Ed.Swarthout@freescale.com> Signed-off-by: Kumar Gala <galak@kernel.crashing.org>
* FSL DDR: Provide a generic set_ddr_laws()Kumar Gala2008-08-27-0/+1
| | | | | | | Provide a helper function that will setup the last available LAWs (upto 2) for DDR. Useful for SPD/dyanmic DDR setting code. Signed-off-by: Kumar Gala <galak@kernel.crashing.org>
* Add proper SPD definitions for DDR1/2/3James Yang2008-08-27-0/+292
| | | | | | Also adds helper functions for DDR1/2 to verify the checksum. Signed-off-by: Kumar Gala <galak@kernel.crashing.org>
* Add support for muas3001 board (MPC8270)Heiko Schocher2008-08-27-0/+387
| | | | Signed-off-by: Heiko Schocher <hs@denx.de>
* fdt: refactor initrd related codeKumar Gala2008-08-26-0/+1
| | | | | | | | | Created a new fdt_initrd() to deal with setting the initrd properties in the device tree and fixing up the mem reserve. We can use this both in the choosen node handling and lets us remove some duplicated code when we fixup the initrd info in bootm on PPC. Signed-off-by: Kumar Gala <galak@kernel.crashing.org>
* fdt: refactor fdt resize codeKumar Gala2008-08-26-0/+1
| | | | | | | Move the fdt resizing code out of ppc specific boot code and into common fdt support code. Signed-off-by: Kumar Gala <galak@kernel.crashing.org>
* bootm: refactor image detection and os load stepsKumar Gala2008-08-26-0/+9
| | | | | | | | | | | | | | Created a bootm_start() that handles the parsing and detection of all the images that will be used by the bootm command (OS, ramdisk, fdt). As part of this we now tract all the relevant image offsets in the bootm_headers_t struct. This will allow us to have all the needed state for future sub-commands and lets us reduce a bit of arch specific code on SPARC. Created a bootm_load_os() that deals with decompression and loading the OS image. Signed-off-by: Kumar Gala <galak@kernel.crashing.org>
* bootm: move lmb into the bootm_headers_t structureKumar Gala2008-08-26-1/+3
| | | | | | | | To allow for persistent state between future bootm subcommands we need the lmb to exist in a global state. Moving it into the bootm_headers_t allows us to do that. Signed-off-by: Kumar Gala <galak@kernel.crashing.org>
* bootm: Set working fdt address as part of the bootm flowKumar Gala2008-08-26-0/+2
| | | | | | | | Set the fdt working address so "fdt FOO" commands can be used as part of the bootm flow. Also set an the environment variable "fdtaddr" with the value. Signed-off-by: Kumar Gala <galak@kernel.crashing.org>
* bootm: refactor fdt locating and relocation codeKumar Gala2008-08-26-0/+13
| | | | | | | Move the code that handles finding a device tree blob and relocating it (if needed) into common code so all arch's have access to it. Signed-off-by: Kumar Gala <galak@kernel.crashing.org>
* bootm: refactor ramdisk locating codeKumar Gala2008-08-26-0/+2
| | | | | | | | Move determing if we have a ramdisk and where its located into the common code. Keep track of the ramdisk start and end in the bootm_headers_t image struct. Signed-off-by: Kumar Gala <galak@kernel.crashing.org>
* bootm: refactor entry point codeKumar Gala2008-08-26-0/+2
| | | | | | | Move entry point code out of each arch and into common code. Keep the entry point in the bootm_headers_t images struct. Signed-off-by: Kumar Gala <galak@kernel.crashing.org>
generated by cgit v1.1 at 2024-10-07 13:38:24 +0000