summaryrefslogtreecommitdiff
path: root/include
diff options
context:
space:
mode:
authorJon Loeliger <jdl@freescale.com>2008-03-18 13:51:06 -0500
committerKumar Gala <galak@kernel.crashing.org>2008-08-27 11:43:50 -0500
commite31d2c1e2bc954dc32e33bb2076139f85b95f8e6 (patch)
tree2bb35a5e0a26ce624c990f618da56193d2f1e124 /include
parentaa11d85cf318b961e029fe50d68ca47d004bce93 (diff)
downloadu-boot-imx-e31d2c1e2bc954dc32e33bb2076139f85b95f8e6.zip
u-boot-imx-e31d2c1e2bc954dc32e33bb2076139f85b95f8e6.tar.gz
u-boot-imx-e31d2c1e2bc954dc32e33bb2076139f85b95f8e6.tar.bz2
FSL DDR: Convert MPC8548CDS to new DDR code.
Signed-off-by: Jon Loeliger <jdl@freescale.com> Signed-off-by: Kumar Gala <galak@kernel.crashing.org>
Diffstat (limited to 'include')
-rw-r--r--include/configs/MPC8548CDS.h37
1 files changed, 20 insertions, 17 deletions
diff --git a/include/configs/MPC8548CDS.h b/include/configs/MPC8548CDS.h
index 33c5c93..ec0b4ff 100644
--- a/include/configs/MPC8548CDS.h
+++ b/include/configs/MPC8548CDS.h
@@ -46,15 +46,7 @@
#define CONFIG_TSEC_ENET /* tsec ethernet support */
#define CONFIG_ENV_OVERWRITE
-#define CONFIG_SPD_EEPROM /* Use SPD EEPROM for DDR setup*/
-#define CONFIG_DDR_DLL /* possible DLL fix needed */
-#undef CONFIG_DDR_2T_TIMING /* Sets the 2T timing bit */
-
-#define CONFIG_DDR_ECC /* only for ECC DDR module */
-#define CONFIG_ECC_INIT_VIA_DDRCONTROLLER /* DDR controller or DMA? */
-#define CONFIG_MEM_INIT_VALUE 0xDeadBeef
#define CONFIG_INTERRUPTS /* enable pci, srio, ddr interrupts */
-
#define CONFIG_FSL_LAW 1 /* Use common FSL init code */
#define CONFIG_FSL_VIA
@@ -67,8 +59,6 @@
*/
#define CONFIG_ASSUME_AMD_FLASH
-#define MPC85xx_DDR_SDRAM_CLK_CNTL /* 85xx has clock control reg */
-
#ifndef __ASSEMBLY__
extern unsigned long get_clock_freq(void);
#endif
@@ -103,17 +93,27 @@ extern unsigned long get_clock_freq(void);
#define CFG_PCI2_ADDR (CFG_CCSRBAR+0x9000)
#define CFG_PCIE1_ADDR (CFG_CCSRBAR+0xa000)
-/*
- * DDR Setup
- */
+/* DDR Setup */
+#define CONFIG_FSL_DDR2
+#undef CONFIG_FSL_DDR_INTERACTIVE
+#define CONFIG_SPD_EEPROM /* Use SPD EEPROM for DDR setup*/
+#define CONFIG_DDR_SPD
+#define CONFIG_DDR_DLL /* possible DLL fix needed */
+
+#undef CONFIG_ECC_INIT_VIA_DDRCONTROLLER /* DDR controller or DMA? */
+#define CONFIG_MEM_INIT_VALUE 0xDeadBeef
+
#define CFG_DDR_SDRAM_BASE 0x00000000 /* DDR is system memory*/
#define CFG_SDRAM_BASE CFG_DDR_SDRAM_BASE
-#define SPD_EEPROM_ADDRESS 0x51 /* DDR DIMM */
+#define CONFIG_NUM_DDR_CONTROLLERS 1
+#define CONFIG_DIMM_SLOTS_PER_CTLR 1
+#define CONFIG_CHIP_SELECTS_PER_CTRL (2 * CONFIG_DIMM_SLOTS_PER_CTLR)
-/*
- * Make sure required options are set
- */
+/* I2C addresses of SPD EEPROMs */
+#define SPD_EEPROM_ADDRESS 0x51 /* CTLR 0 DIMM 0 */
+
+/* Make sure required options are set */
#ifndef CONFIG_SPD_EEPROM
#error ("CONFIG_SPD_EEPROM is required")
#endif
@@ -342,6 +342,9 @@ extern unsigned long get_clock_freq(void);
#define CONFIG_OF_BOARD_SETUP 1
#define CONFIG_OF_STDOUT_VIA_ALIAS 1
+#define CFG_64BIT_VSPRINTF 1
+#define CFG_64BIT_STRTOUL 1
+
/*
* I2C
*/