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* fsl-ddr: setup ODT_RD_CFG & ODT_WR_CFG when we interleaveDave Liu2010-01-05-0/+3
* fsl-ddr: add override for the Rtt_WrDave Liu2010-01-05-3/+7
* fsl-ddr: add the override for write levelingDave Liu2010-01-05-6/+15
* fsl-ddr: Fix power-down timing settingsDave Liu2010-01-05-3/+4
* ppc/8xxx: Remove is_fsl_pci_agentKumar Gala2010-01-05-41/+3
* ppc/8xxx: Don't use pci_cfg on FSL_CORENET platformsKumar Gala2010-01-05-0/+3
* fsl-ddr: Fix the chip-select interleaving issueDave Liu2009-11-12-4/+3
* mpc8xxx: improve LAW error messages when setting up DDRPaul Gortmaker2009-10-16-4/+5
* ppc/p4080: Add various p4080 related defines (and p4040)Kumar Gala2009-09-24-0/+4
* ppc/8xxx: Misc DDR related fixesKumar Gala2009-09-15-7/+7
* ppc/85xx/86xx: Bug fix: call to puts in probecpu() moved to checkcpu().Poonam Aggrwal2009-09-08-6/+0
* ppc/85xx/86xx: Device tree fixup for number of coresPoonam Aggrwal2009-09-08-0/+56
* ppc/85xx,86xx: Handling Unknown SOC versionPoonam Aggrwal2009-09-08-2/+3
* ppc/8xxx: Refactor code to determine if PCI is enabled & agent/hostKumar Gala2009-09-08-0/+226
* ppc/8xxx: Remove ddr_pd_cntl register since it doesn't existKumar Gala2009-09-08-23/+0
* 85xx: Added single core members of FSL P1xx/P2xx processors seriesPoonam Aggrwal2009-08-28-2/+6
* 85xx: Added P1020 Processor Support.Poonam Aggrwal2009-08-28-0/+2
* 8xxx: Removed CONFIG_NUM_CPUS from 85xx/86xxPoonam Aggrwal2009-08-28-34/+59
* 8xxx: Refactored common cpu specific code for 85xx/86xx into one file.Poonam Aggrwal2009-08-28-0/+131
* 85xx, 86xx: Add common board_add_ram_info()Peter Tyser2009-07-22-41/+98
* fsl_ddr: Fix DDR3 calculation of rank density with 8GB or moreTimur Tabi2009-07-01-1/+1
* fsl-ddr: Fix handling of >4G of memory when !CONFIG_PHYS_64BITKumar Gala2009-06-12-39/+41
* fsl-ddr: add the DDR3 SPD infrastructureDave Liu2009-03-30-46/+754
* fsl-ddr: Fix two bugs in the ddr infrastructureDave Liu2009-03-30-1/+4
* fsl-ddr: Allow system to boot if we have more than 4G of memoryKumar Gala2009-02-16-1/+1
* fsl-ddr: ignore memctl_intlv_ctl setting if only one DDR controllerKumar Gala2009-02-16-0/+4
* fsl-ddr: use the 1T timing as default configurationDave Liu2009-01-23-1/+1
* fsl-ddr: make the self refresh idle threshold configurableDave Liu2009-01-23-4/+8
* fsl-ddr: clean up the ddr code for DDR3 controllerDave Liu2009-01-23-11/+13
* fsl-ddr: update the bit mask for DDR3 controllerDave Liu2009-01-23-4/+8
* fsl ddr skip interleaving if not supported.Ed Swarthout2008-12-03-12/+17
* Add debug information for DDR controller registersHaiying Wang2008-10-18-0/+13
* Check DDR interleaving modeHaiying Wang2008-10-18-5/+112
* Pass dimm parameters to populate populate controller optionsHaiying Wang2008-10-18-87/+7
* Make DDR interleaving mode work correctlyHaiying Wang2008-10-18-12/+54
* rename CFG_ macros to CONFIG_SYSJean-Christophe PLAGNIOL-VILLARD2008-10-18-7/+7
* Coding style cleanup, update CHANGELOGWolfgang Denk2008-09-13-15/+15
* Fix compiler warning in mpc8xxx ddr codeKumar Gala2008-09-07-2/+4
* FSL DDR: Add DDR2 DIMM paramter supportKumar Gala2008-08-27-0/+339
* FSL DDR: Add DDR1 DIMM paramter supportKumar Gala2008-08-27-0/+343
* FSL DDR: Rewrite the FSL mpc8xxx DDR controller setup code.Kumar Gala2008-08-27-0/+2418
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