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* armv8: fsl-layerscale: Rewrite reserving memory for MC and debug serverYork Sun2015-12-15-51/+0
| | | | | | | | | | | MC and debug server are not board-specific. Move reserving memory to SoC file, using the new board_reserve_ram_top function. Reduce debug server memory by 2MB to make room for secure memory. In the system with MC and debug server, the top of u-boot memory is not the end of memory. PRAM is not used for this reservation. Signed-off-by: York Sun <yorksun@freescale.com>
* armv8: fsl-layerscape: Make DDR non secure in MMU tablesYork Sun2015-12-15-0/+69
| | | | | | | | | | | | | | | | | | | DDR has been set as secure in MMU tables. Non-secure master such as SDHC DMA cannot access data correctly. Mixing secure and non- secure MMU entries requirs the MMU tables themselves in secure memory. This patch moves MMU tables into a secure DDR area. Early MMU tables are changed to set DDR as non-secure. A new table is added into final MMU tables so secure memory can have 2MB granuality. gd->secure_ram tracks the location of this secure memory. For ARMv8 SoCs, the RAM base is not zero and RAM is divided into several banks. gd->secure_ram needs to be maintained before using. This maintenance is board-specific, depending on the SoC and memory bank of the secure memory falls into. Signed-off-by: York Sun <yorksun@freescale.com>
* arm: ls1021a: merge SoC specific code in a separate fileYao Yuan2015-12-13-87/+4
| | | | | | | Create a soc.c file to put the code for soc special settings. Signed-off-by: Yuan Yao <yao.yuan@freescale.com> Reviewed-by: York Sun <yorksun@freescale.com>
* armv8/ls1043ardb: Add support for >2GB memoryShaohui Xie2015-12-13-1/+18
| | | | | | | | This patch also expose the complete DDR region(s) to Linux. Signed-off-by: Shaohui Xie <Shaohui.Xie@freescale.com> Signed-off-by: Mingkai Hu <Mingkai.Hu@freescale.com> Reviewed-by: York Sun <yorksun@freescale.com>
* freescale: fman: make sure phy-handle property is big endianShaohui Xie2015-12-13-0/+2
| | | | | | | | | | When creating phy-handle property, an unsigned int value is created by fdt_create_phandle, and memcpy is used to get the value, since DTS is big endian, the value cannot be used directly on little endian SoCs, it should be converted by cpu_to_fdt32. Signed-off-by: Shaohui Xie <Shaohui.Xie@freescale.com> Reviewed-by: York Sun <yorksun@freescale.com>
* armv8/ls2080ardb: Update DDR settings for four chip-select caseYork Sun2015-12-13-4/+12
| | | | | | | When 4 chip-selects are used, vref should use range 1 and CDT uses 80 ohm, and 2T timing is enabled. Signed-off-by: York Sun <yorksun@freescale.com>
* armv8/ls2080aqds: Update DDR settings for four chip-select caseYork Sun2015-12-13-4/+12
| | | | | | | When 4 chip-selects are used, vref should use range 1 and CDT uses 80 ohm, and 2T timing is enabled. Signed-off-by: York Sun <yorksun@freescale.com>
* imx: mx7dsabresd: Add QSPI supportPeng Fan2015-12-11-0/+30
| | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | Support qspi flashes for mx7dsabresd 1. introduce pin mux settings 2. enable qspi clock 3. introduce related macro definitions Default QSPI is not enabled, since we need hardware rework to use QSPI, see SPF-28590, page 9: " QSPI signals are muxed with EPDC_D[7:0] When using QSPI: de-populate R388-R391, R396-R399 populate R392-R395, R299, R300 " After hardware rework, define CONFIG_FSL_QSPI in mx7dsabresd.h. qspi flashes can be deteced and read/erase/write. Log info: " => sf probe SF: Detected MX25L51235F with page size 256 Bytes, erase size 64 KiB, total 64 MiB => sf read 0x80000000 0 0x4000000 device 0 whole chip SF: 67108864 bytes @ 0x0 Read: OK => sf erase 0 0x4000000 SF: 67108864 bytes @ 0x0 Erased: OK => sf write 0x80000000 0 0x4000000 device 0 whole chip SF: 67108864 bytes @ 0x0 Written: OK " Cc: Fabio Estevam <fabio.estevam@freescale.com> Cc: Adrian Alonso <aalonso@freescale.com> Reviewed-by: Stefano Babic <sbabic@denx.de> Reviewed-by: Jagan Teki <jteki@openedev.com> Signed-off-by: Peng Fan <Peng.Fan@freescale.com>
* board/ls2080qds: Fix typo in README for QSGMII riser cardPrabhakar Kushwaha2015-11-30-1/+1
| | | | | | | | | | DPMACx to PHY mapping for SGMII is mentioned as QSGMII. So fix typo in README for QSGMII rise card. Signed-off-by: Prabhakar Kushwaha <prabhakar@freescale.com> [York Sun: Change from ls2085aqds to ls2080aqds] Reviewed-by: York Sun <yorksun@freescale.com>
* armv8/ls1043ardb: add USB supportGong Qianyu2015-11-30-0/+16
| | | | | | | Add support for the third USB controller for LS1043A. Signed-off-by: Gong Qianyu <Qianyu.Gong@freescale.com> Reviewed-by: York Sun <yorksun@freescale.com>
* armv8/ls1043aqds: add LS1043AQDS board supportShaohui Xie2015-11-30-0/+1235
| | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | LS1043AQDS Specification: ------------------------- Memory subsystem: * 2GByte DDR4 DIMM * 128 Mbyte NOR flash single-chip memory * 512 Mbyte NAND flash * 16 Mbyte high-speed SPI flash * SD connector to interface with the SD memory card Ethernet: * Two RGMII ports * XFI 10G port * SGMII * QSGMII with 4x 1G ports PCIe: supports Gen 1 and Gen 2 SATA 3.0: one SATA 3.0 port USB 3.0: two micro AB connector and one type A connector UART: supports two UARTs up to 115200 bps for console Signed-off-by: Shaohui Xie <Shaohui.Xie@freescale.com> Signed-off-by: Mingkai Hu <Mingkai.Hu@freescale.com> Signed-off-by: Hou Zhiqiang <B48286@freescale.com> Signed-off-by: Gong Qianyu <Qianyu.Gong@freescale.com> [York Sun: Add CONFIG_SYS_NS16550=y in defconfig] Reviewed-by: York Sun <yorksun@freescale.com>
* armv8: ls2085a: Add support of LS2085A SoCPrabhakar Kushwaha2015-11-30-0/+6
| | | | | | | | | | | | | Freescale's LS2085A is a another personality of LS2080A SoC with support of AIOP and DP-DDR. This Patch adds support of LS2085A Personality. Signed-off-by: Pratiyush Mohan Srivastava <pratiyush.srivastava@freescale.com> Signed-off-by: Prabhakar Kushwaha <prabhakar@freescale.com> [York Sun: Updated MAINTAINERS files Dropped #ifdef in cpu.h Add CONFIG_SYS_NS16550=y in defconfig] Reviewed-by: York Sun <yorksun@freescale.com>
* armv8: LS2080A: Rename LS2085A to reflect LS2080APrabhakar Kushwaha2015-11-30-113/+126
| | | | | | | | | | | LS2080A is a prime personality of Freescale’s LS2085A. It is a non-AIOP personality without support of DP-DDR, L2 switch, 1588, PCIe endpoint etc. So renaming existing LS2085A code base to reflect LS2080A (Prime personality) Signed-off-by: Pratiyush Mohan Srivastava <pratiyush.srivastava@freescale.com> Signed-off-by: Prabhakar Kushwaha <prabhakar@freescale.com> [York Sun: Dropped #ifdef in cpu.c for cpu_type_list] Reviewed-by: York Sun <yorksun@freescale.com>
* driver: net: fsl-mc: Create DPAA2 object at run-timePrabhakar Kushwaha2015-11-30-2/+8
| | | | | | | | | | Freescale's DPAA2 ethernet driver depends upon the static DPL for the DPRC, DPNI, DPBP, DPIO objects. Instead of static objects, Create DPNI, DPBP, DPIO objects at run-time. Signed-off-by: Prabhakar Kushwaha <prabhakar@freescale.com> Reviewed-by: York Sun <yorksun@freescale.com>
* armv8: ls2085aqds: Print function name during SerDes errorPrabhakar Kushwaha2015-11-30-8/+8
| | | | | | | | Print function name along with SerDes Protocol during SerDes Protocol not supported error. Signed-off-by: Prabhakar Kushwaha <prabhakar@freescale.com> Reviewed-by: York Sun <yorksun@freescale.com>
* Move console definitions into a new console.h fileSimon Glass2015-11-19-0/+13
| | | | | | | | The console includes a global variable and several functions that are only used by a small subset of U-Boot files. Before adding more functions, move the definitions into their own header file. Signed-off-by: Simon Glass <sjg@chromium.org>
* imx: mx7dsabresd: support lcdifPeng Fan2015-11-12-0/+64
| | | | | | | | | | | Support LCDIF for mx7dsabresd board: 1. Add pinmux settings 2. Add VIDEO related macro definition and videomode env settings. Signed-off-by: Peng Fan <Peng.Fan@freescale.com> Cc: Stefano Babic <sbabic@denx.de> Cc: Fabio Estevam <fabio.estevam@freescale.com> Cc: Adrian Alonso <aalonso@freescale.com>
* imx: mx6ul_14x14_evk: support lcdif displayPeng Fan2015-11-12-0/+63
| | | | | | | | | | | | | Support lcdif display: 1. Add pinmux and pad settings for LCDIF 2. Introduce setup_lcd to do the settings for LCDIF 3. Enable VIDEO related macros in board header files 4. Add a new env videomode which is needed by mxsfb.c. The settings for videomode in this patch is for TFT43AB. 5. Tested on mx6ul 14x14/9x9 evk. Signed-off-by: Peng Fan <Peng.Fan@freescale.com> Cc: Stefano Babic <sbabic@denx.de>
* mx6ul_14x14_evk: Remove empty reset_cpu()Fabio Estevam2015-11-12-4/+0
| | | | | | | There is really no need to provide an empty reset_cpu() implementation, so just remove it. Signed-off-by: Fabio Estevam <fabio.estevam@freescale.com>
* mx6sxsabresd: Remove empty reset_cpu()Fabio Estevam2015-11-12-4/+0
| | | | | | | There is really no need to provide an empty reset_cpu() implementation, so just remove it. Signed-off-by: Fabio Estevam <fabio.estevam@freescale.com>
* mx6slevk: Remove empty reset_cpu()Fabio Estevam2015-11-12-4/+0
| | | | | | | There is really no need to provide an empty reset_cpu() implementation, so just remove it. Signed-off-by: Fabio Estevam <fabio.estevam@freescale.com>
* mx6sabresd: Remove empty reset_cpu()Fabio Estevam2015-11-12-4/+0
| | | | | | | | There is really no need to provide an empty reset_cpu() implementation, so just remove it. Signed-off-by: Fabio Estevam <fabio.estevam@freescale.com> Reviewed-by: Stefano Babic <sbabic@denx.de>
* Merge git://git.denx.de/u-bootStefano Babic2015-11-12-253/+944
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| * ls1043ardb: Add missing config entries to MAINTAINERSFabio Estevam2015-11-10-0/+2
| | | | | | | | | | | | | | | | | | ls1043ardb_nand_defconfig and ls1043ardb_sdcard_defconfig are missing in the MAINTAINERS file, so add them for completeness. Reported-by: Albert Aribaud <albert.u.boot@aribaud.net> Signed-off-by: Fabio Estevam <fabio.estevam@freescale.com> Reviewed-by: Albert ARIBAUD <albert.u.boot@aribaud.net>
| * mmc: fsl_esdhc: enable EVDD automatic control for SD/MMC Legacy Adapter CardYangbo Lu2015-11-02-0/+3
| | | | | | | | | | | | | | | | | | When detecting SDHC Adapter Card Type 2(SD/MMC Legacy Adapter Card), enable EVDD automatic control via SDHC_VS. This could support SD card IO voltage switching for UHS-1 speed mode. Signed-off-by: Yangbo Lu <yangbo.lu@freescale.com> Reviewed-by: York Sun <yorksun@freescale.com>
| * mmc: fsl_esdhc: enable dat[4:7] for eMMC4.5 Adapter CardYangbo Lu2015-11-02-0/+2
| | | | | | | | | | | | | | | | If adapter card type identification is supported for platform, we would enable dat[4:7] for eMMC4.5 Adapter Card. Signed-off-by: Yangbo Lu <yangbo.lu@freescale.com> Reviewed-by: York Sun <yorksun@freescale.com>
| * t1040d4rdb: assign muxed pins to qe-tdm when set hwconfig qe-tdmZhao Qiang2015-11-02-0/+11
| | | | | | | | | | | | | | | | | | qe-tdm is muxed with diu, if hwconfig setted as qe-tdm, assign muxed pins to qe-tdm, then delete diu node from device tree. Signed-off-by: Zhao Qiang <qiang.zhao@freescale.com> Reviewed-by: York Sun <yorksun@freescale.com>
| * arm: ls1021atwr: optimize the deep sleep latencytang yuantian2015-10-30-6/+17
| | | | | | | | | | | | | | | | | | | | | | | | It will take more than 1s when wake up from deep sleep. Most of the time is spent on outputing information. This patch reduced the deep sleep latency by: 1. avoid outputing system informaton 2. remove flush cache after DDR restore 3. skip reloading second stage uboot binary when SD boot Signed-off-by: Tang Yuantian <Yuantian.Tang@freescale.com> Reviewed-by: York Sun <yorksun@freescale.com>
| * SECURE_BOOT: Correct reading of ITS bitAneesh Bansal2015-10-30-1/+1
| | | | | | | | | | | | | | | | | | The ITS bit was being read incorrectly beacause of operator precedence. The same ahs been corrected. Signed-off-by: Lawish Deshmukh <lawish.deshmukh@freescale.com> Signed-off-by: Aneesh Bansal <aneesh.bansal@freescale.com> Reviewed-by: York Sun <yorksun@freescale.com>
| * arm: ls1021a: Add sata support on qds and twr boardtang yuantian2015-10-29-0/+24
| | | | | | | | | | | | | | | | | | | | Freescale ARM-based Layerscape LS102xA contain a SATA controller which comply with the serial ATA 3.0 specification and the AHCI 1.3 specification. This patch adds SATA feature on ls1021aqds and ls1021atwr boards. Signed-off-by: Tang Yuantian <Yuantian.Tang@freescale.com> Reviewed-by: York Sun <yorksun@freescale.com>
| * armv8/ls1043ardb: Add sd boot supportGong Qianyu2015-10-29-0/+33
| | | | | | | | | | Signed-off-by: Gong Qianyu <Qianyu.Gong@freescale.com> Reviewed-by: York Sun <yorksun@freescale.com>
| * armv8/ls1043ardb: esdhc: Add esdhc support for ls1043ardbYangbo Lu2015-10-29-0/+1
| | | | | | | | | | | | | | | | This patch adds esdhc support for ls1043ardb. Signed-off-by: Yangbo Lu <yangbo.lu@freescale.com> Signed-off-by: Gong Qianyu <Qianyu.Gong@freescale.com> Reviewed-by: York Sun <yorksun@freescale.com>
| * armv8/ls1043a: Add Fman supportShaohui Xie2015-10-29-1/+87
| | | | | | | | | | | | | | | | Signed-off-by: Hou Zhiqiang <B48286@freescale.com> Signed-off-by: Shaohui Xie <Shaohui.Xie@freescale.com> Signed-off-by: Mingkai Hu <Mingkai.Hu@freescale.com> Signed-off-by: Gong Qianyu <Qianyu.Gong@freescale.com> Reviewed-by: York Sun <yorksun@freescale.com>
| * armv8/ls1043ardb: Add nand boot supportGong Qianyu2015-10-29-0/+42
| | | | | | | | | | | | | | | | Signed-off-by: Gong Qianyu <Qianyu.Gong@freescale.com> Signed-off-by: Hou Zhiqiang <B48286@freescale.com> Signed-off-by: Shaohui Xie <Shaohui.Xie@freescale.com> Signed-off-by: Mingkai Hu <Mingkai.Hu@freescale.com> Reviewed-by: York Sun <yorksun@freescale.com>
| * armv8/ls1043ardb: Add LS1043ARDB board supportMingkai Hu2015-10-29-0/+642
| | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | LS1043ARDB Specification: ------------------------- Memory subsystem: * 2GByte DDR4 SDRAM (32bit bus) * 128 Mbyte NOR flash single-chip memory * 512 Mbyte NAND flash * 16 Mbyte high-speed SPI flash * SD connector to interface with the SD memory card Ethernet: * XFI 10G port * QSGMII with 4x 1G ports * Two RGMII ports PCIe: * PCIe2 (Lanes C) to mini-PCIe slot * PCIe3 (Lanes D) to PCIe slot USB 3.0: two super speed USB 3.0 type A ports UART: supports two UARTs up to 115200 bps for console Signed-off-by: Hou Zhiqiang <B48286@freescale.com> Signed-off-by: Li Yang <leoli@freescale.com> Signed-off-by: Mingkai Hu <Mingkai.Hu@freescale.com> Signed-off-by: York Sun <yorksun@freescale.com> Signed-off-by: Gong Qianyu <Qianyu.Gong@freescale.com>
| * armv8/fsl_lsch3: Change arch to fsl-layerscapeMingkai Hu2015-10-29-9/+7
| | | | | | | | | | | | | | | | | | | | | | | | | | There are two LS series processors are built on ARMv8 Layersacpe architecture currently, LS2085A and LS1043A. They are based on ARMv8 core although use different chassis, so create fsl-layerscape to refactor the common code for the LS series processors which also paves the way for adding LS1043A platform. Signed-off-by: Mingkai Hu <Mingkai.Hu@freescale.com> Signed-off-by: Hou Zhiqiang <B48286@freescale.com> Signed-off-by: Gong Qianyu <Qianyu.Gong@freescale.com> Reviewed-by: York Sun <yorksun@freescale.com>
| * net: Move some header files to include/Shaohui Xie2015-10-29-14/+14
| | | | | | | | | | | | | | | | | | | | The fsl_dtsec.h & fsl_tgec.h & fsl_fman.h can be shared on both ARM and PPC, move it out of ppc to include/, and change the path in drivers accordingly. Signed-off-by: Shaohui Xie <Shaohui.Xie@freescale.com> Signed-off-by: Gong Qianyu <Qianyu.Gong@freescale.com> Reviewed-by: York Sun <yorksun@freescale.com>
| * armv7/ls1021a: move ns_access to common fileMingkai Hu2015-10-29-190/+23
| | | | | | | | | | | | | | | | | | | | Config Security Level Register is different between different SoCs, so put the CSL register definition into the arch specific directory. Signed-off-by: Mingkai Hu <Mingkai.Hu@freescale.com> Signed-off-by: Hou Zhiqiang <B48286@freescale.com> Signed-off-by: Gong Qianyu <Qianyu.Gong@freescale.com> Reviewed-by: York Sun <yorksun@freescale.com>
| * Pointers in ESBC header made 32 bitAneesh Bansal2015-10-29-10/+10
| | | | | | | | | | | | | | | | | | | | For the Chain of Trust, the esbc_validate command supports 32 bit fields for location of the image. In the header structure definition, these were declared as pointers which made them 64 bit on a 64 bit core. Signed-off-by: Aneesh Bansal <aneesh.bansal@freescale.com> Reviewed-by: York Sun <yorksun@freescale.com>
| * arm: ls1021a: Add QSPI or IFC support in SD bootAlison Wang2015-10-26-22/+25
| | | | | | | | | | | | | | | | | | | | | | | | | | | | As QSPI and IFC are pin-multiplexed on LS1021A, only IFC is supported in SD boot now. For the customer's demand, QSPI needs to be supported in SD boot too. This patch adds QSPI or IFC support in SD boot according to the corresponding defconfig. For detail, ls1021atwr_sdcard_ifc_defconfig is used to support IFC in SD boot and ls1021atwr_sdcard_qspi_defconfig is used to support QSPI in SD boot. Signed-off-by: Alison Wang <alison.wang@freescale.com> Reviewed-by: York Sun <yorksun@freescale.com>
| * vf610twr: Fix typo in DRAM initAnthony Felice2015-10-16-1/+1
| | | | | | | | | | | | | | | | | | This commit fixes a typo in vf610twr DRAM init that was causing a hang in U-Boot for the Vybrid Tower. This typo was introduced in commit 3f353cecc (vf610: refactor DDRMC code). Signed-off-by: Anthony Felice <tony.felice@timesys.com> Reviewed-by: Fabio Estevam <fabio.estevam@freescale.com>
* | mx7dsabresd: add secure boot supportAdrian Alonso2015-10-30-0/+7
| | | | | | | | | | | | Add secure boot support for mx7dsabresd target board Signed-off-by: Adrian Alonso <aalonso@freescale.com>
* | imx: mx6sabresd: add i.MX6DQP Sabresd supportPeng Fan2015-10-30-6/+63
| | | | | | | | | | | | | | | | | | | | Add i.MX6DQP-Sabresd board support: 1. set fdt_file according to board_rev which is set at runtime. 2. Add mx6dqp_ddr_ioregs and calibration value for this board. Signed-off-by: Peng Fan <Peng.Fan@freescale.com> Cc: Stefano Babic <sbabic@denx.de> Cc: Fabio Estevam <fabio.estevam@freescale.com>
* | vf610twr: Fix typo in DRAM initAnthony Felice2015-10-16-1/+1
|/ | | | | | | | | This commit fixes a typo in vf610twr DRAM init that was causing a hang in U-Boot for the Vybrid Tower. This typo was introduced in commit 3f353cecc (vf610: refactor DDRMC code). Signed-off-by: Anthony Felice <tony.felice@timesys.com> Reviewed-by: Fabio Estevam <fabio.estevam@freescale.com>
* vf610: refactor DDRMC codeAlbert ARIBAUD \\(3ADEV\\)2015-10-02-51/+105
| | | | | | | | The VF610 DDRMC driver code contains settings which are board-specific. Move these out to boards so that new boards can define their own without having to modify the driver. Signed-off-by: Albert ARIBAUD (3ADEV) <albert.aribaud@3adev.fr>
* imx: mx7dsabresd: drop code for CONFIG_CMD_BMODEPeng Fan2015-09-24-14/+0
| | | | | | | | | We use outer pmic reset and drop internal reset signal, bmode will not work as expected, so drop boot mode code for 7dsabresd board. Signed-off-by: Peng Fan <Peng.Fan@freescale.com> Cc: Stefano Babic <sbabic@denx.de> Cc: Adrian Alonso <aalonso@freescale.com>
* imx: boards: Add maintainers infoPeng Fan2015-09-24-0/+5
| | | | | | | Add MAINTAINERS info for mx6slevk_spl, mx6ul_9x9_evk and mx6qpsabreauto. Signed-off-by: Peng Fan <Peng.Fan@freescale.com> Cc: Stefano Babic <sbabic@denx.de>
* imx: mx7dsabresd: drop SYS_SOC from board KconfigPeng Fan2015-09-20-3/+0
| | | | | | | | We have defined this kconfig entry in arch/arm/cpu/armv7/mx7/Kconfig, no need to redefine it in board Kconfig. Signed-off-by: Peng Fan <Peng.Fan@freescale.com> Cc: Stefano Babic <sbabic@denx.de>
* mx6ul_14x14_evk: Remove get_board_rev()Fabio Estevam2015-09-20-5/+0
| | | | | | | | | | | get_board_rev() is not actually providing the board revision. It just returns the CPU revision instead. As the CPU revision is already printed on boot, there is no reason to have get_board_rev(), so let's remove it. Signed-off-by: Fabio Estevam <fabio.estevam@freescale.com>
* mx6ul_14x14_evk: Staticize when possibleFabio Estevam2015-09-20-2/+2
| | | | | | | | Make the internal symbols static when possible. This prevents sparse build warnings. Signed-off-by: Fabio Estevam <fabio.estevam@freescale.com>
generated by cgit v1.1 at 2024-11-08 15:46:39 +0000