diff options
| author | Gong Qianyu <Qianyu.Gong@freescale.com> | 2015-10-26 19:47:53 +0800 |
|---|---|---|
| committer | York Sun <yorksun@freescale.com> | 2015-10-29 10:34:01 -0700 |
| commit | 3ad447292304657aaf9c4a36f7eae34f449c5dbd (patch) | |
| tree | 3e7eb3f74a3d11a37dd1c51bf69f91b9da81a046 /board/freescale | |
| parent | f3a8e2b7d41ca9039e934b5a59899dd57c577fa3 (diff) | |
| download | u-boot-imx-3ad447292304657aaf9c4a36f7eae34f449c5dbd.zip u-boot-imx-3ad447292304657aaf9c4a36f7eae34f449c5dbd.tar.gz u-boot-imx-3ad447292304657aaf9c4a36f7eae34f449c5dbd.tar.bz2 | |
armv8/ls1043ardb: Add nand boot support
Signed-off-by: Gong Qianyu <Qianyu.Gong@freescale.com>
Signed-off-by: Hou Zhiqiang <B48286@freescale.com>
Signed-off-by: Shaohui Xie <Shaohui.Xie@freescale.com>
Signed-off-by: Mingkai Hu <Mingkai.Hu@freescale.com>
Reviewed-by: York Sun <yorksun@freescale.com>
Diffstat (limited to 'board/freescale')
| -rw-r--r-- | board/freescale/ls1043ardb/README | 1 | ||||
| -rw-r--r-- | board/freescale/ls1043ardb/cpld.c | 19 | ||||
| -rw-r--r-- | board/freescale/ls1043ardb/cpld.h | 1 | ||||
| -rw-r--r-- | board/freescale/ls1043ardb/ls1043ardb_pbi.cfg | 14 | ||||
| -rw-r--r-- | board/freescale/ls1043ardb/ls1043ardb_rcw_nand.cfg | 7 |
5 files changed, 42 insertions, 0 deletions
diff --git a/board/freescale/ls1043ardb/README b/board/freescale/ls1043ardb/README index d5925a9..4f15557 100644 --- a/board/freescale/ls1043ardb/README +++ b/board/freescale/ls1043ardb/README @@ -83,3 +83,4 @@ Start Address End Address Description Size Booting Options --------------- a) NOR boot +b) NAND boot diff --git a/board/freescale/ls1043ardb/cpld.c b/board/freescale/ls1043ardb/cpld.c index 3f1101e..f29383d 100644 --- a/board/freescale/ls1043ardb/cpld.c +++ b/board/freescale/ls1043ardb/cpld.c @@ -45,6 +45,22 @@ void cpld_set_defbank(void) CPLD_WRITE(global_rst, 1); } +void cpld_set_nand(void) +{ + u16 reg = CPLD_CFG_RCW_SRC_NAND; + u8 reg5 = (u8)(reg >> 1); + u8 reg6 = (u8)(reg & 1); + + cpld_rev_bit(®5); + + CPLD_WRITE(soft_mux_on, 1); + + CPLD_WRITE(cfg_rcw_src1, reg5); + CPLD_WRITE(cfg_rcw_src2, reg6); + + CPLD_WRITE(system_rst, 1); +} + #ifdef DEBUG static void cpld_dump_regs(void) { @@ -91,6 +107,8 @@ int do_cpld(cmd_tbl_t *cmdtp, int flag, int argc, char * const argv[]) if (strcmp(argv[1], "reset") == 0) { if (strcmp(argv[2], "altbank") == 0) cpld_set_altbank(); + else if (strcmp(argv[2], "nand") == 0) + cpld_set_nand(); else cpld_set_defbank(); #ifdef DEBUG @@ -109,6 +127,7 @@ U_BOOT_CMD( "Reset the board or alternate bank", "reset: reset to default bank\n" "cpld reset altbank: reset to alternate bank\n" + "cpld reset nand: reset to boot from NAND flash\n" #ifdef DEBUG "cpld dump - display the CPLD registers\n" #endif diff --git a/board/freescale/ls1043ardb/cpld.h b/board/freescale/ls1043ardb/cpld.h index ea4efd8..5f43a8a 100644 --- a/board/freescale/ls1043ardb/cpld.h +++ b/board/freescale/ls1043ardb/cpld.h @@ -40,4 +40,5 @@ void cpld_rev_bit(unsigned char *value); #define CPLD_SW_MUX_BANK_SEL 0x40 #define CPLD_BANK_SEL_MASK 0x07 #define CPLD_BANK_SEL_ALTBANK 0x04 +#define CPLD_CFG_RCW_SRC_NAND 0x106 #endif diff --git a/board/freescale/ls1043ardb/ls1043ardb_pbi.cfg b/board/freescale/ls1043ardb/ls1043ardb_pbi.cfg new file mode 100644 index 0000000..f072274 --- /dev/null +++ b/board/freescale/ls1043ardb/ls1043ardb_pbi.cfg @@ -0,0 +1,14 @@ +#Configure Scratch register +09570600 00000000 +09570604 10000000 +#Alt base register +09570158 00001000 +#Disable CCI barrier tranaction +09570178 0000e010 +09180000 00000008 +#USB PHY frequency sel +09570418 0000009e +0957041c 0000009e +09570420 0000009e +#flush PBI data +096100c0 000fffff diff --git a/board/freescale/ls1043ardb/ls1043ardb_rcw_nand.cfg b/board/freescale/ls1043ardb/ls1043ardb_rcw_nand.cfg new file mode 100644 index 0000000..935ffc0 --- /dev/null +++ b/board/freescale/ls1043ardb/ls1043ardb_rcw_nand.cfg @@ -0,0 +1,7 @@ +#PBL preamble and RCW header +aa55aa55 01ee0100 +# serdes protocol +0810000f 0c000000 00000000 00000000 +14550002 80004012 e0106000 61002000 +00000000 00000000 00000000 00038800 +00000000 00001100 00000096 00000001 |