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authorAnthony Felice <tony.felice@timesys.com>2015-10-09 16:38:39 -0400
committerTom Rini <trini@konsulko.com>2015-10-16 07:21:09 -0400
commit4b8cdd484c51bb05b47cc83c634ba4a4043aa997 (patch)
treefb97ab8c3ef8d2fd317b20036298910fdef88b6c /board/freescale
parenta7e2c6f6bb0b28d5b7f08bf407742fc3fddf701b (diff)
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vf610twr: Fix typo in DRAM init
This commit fixes a typo in vf610twr DRAM init that was causing a hang in U-Boot for the Vybrid Tower. This typo was introduced in commit 3f353cecc (vf610: refactor DDRMC code). Signed-off-by: Anthony Felice <tony.felice@timesys.com> Reviewed-by: Fabio Estevam <fabio.estevam@freescale.com>
Diffstat (limited to 'board/freescale')
-rw-r--r--board/freescale/vf610twr/vf610twr.c2
1 files changed, 1 insertions, 1 deletions
diff --git a/board/freescale/vf610twr/vf610twr.c b/board/freescale/vf610twr/vf610twr.c
index 7834931..37b241d 100644
--- a/board/freescale/vf610twr/vf610twr.c
+++ b/board/freescale/vf610twr/vf610twr.c
@@ -108,7 +108,7 @@ int dram_init(void)
.trcd_int = 6,
.tras_lockout = 0,
.tdal = 12,
- .bstlen = 0,
+ .bstlen = 3,
.tdll = 512,
.trp_ab = 6,
.tref = 3120,