| Commit message (Collapse) | Author | Age | Lines |
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VGEN3 and VGEN5 have been fused the right value in PF0100 on i.mx6qp board,
so software didn't need to change their voltage output anymore. Otherwise,
VGEN3 will be wrongly updated from 1.8v to 2.8v.
Signed-off-by: Robin Gong <yibin.gong@nxp.com>
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We found a issue in PLL6 ENET that changing the bit[1:0] DIV_SELECT for ENET
ref clock will impact the SATA ref 100Mhz clock. If SATA is initialized before
this changing, SATA read/write can't work after it. And we have to re-init SATA.
The issue can reproduce on both i.MX6DQP and i.MX6DQ. IC investigation is ongoing.
This patch is an work around that moves the ENET clock setting
(enable_fec_anatop_clock) from ethernet init to board_init which is prior
than SATA initialization. So there is no PLL6 change after SATA init.
Signed-off-by: Ye Li <ye.li@nxp.com>
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In u-boot, i.MX6QP sabresd board uses 125Mhz ref clock from PHY,
While kernel uses the clock from internal PLL by setting GPR5 bit 9.
When doing warm reset in kernel, the GPR regigster is not reset, so
the clock source still is the PLL. This causes ENET in u-boot can't work.
In this patch, we change the u-boot to use internal PLL to align with
kernel for i.MX6QP. This also fixes the ENET issue after kernel warm reset.
Signed-off-by: Ye Li <ye.li@nxp.com>
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For i.MX6QP, the QoS settings is different from others. Align with DCD.
Signed-off-by: Peng Fan <peng.fan@nxp.com>
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DDR script file:
arik_r2_sdb_ddr3_528_1.14.inc
Compass link:
http://compass.freescale.net/livelink/livelink?func=ll&objid=235302593&objAction=browse&sort=name&viewType=1
Update:
setmem /32 0x020e0534 = 0x00018200 // IOMUXC_SW_PAD_CTL_PAD_DRAM_ADDR02 (SDQS0_B_TRIM=01, SDQS0_TRIM=10)
setmem /32 0x020e0538 = 0x00008000 // IOMUXC_SW_PAD_CTL_PAD_DRAM_ADDR03 (SDQS1_B_TRIM=00, SDQS1_TRIM=00)
setmem /32 0x020e053C = 0x00018200 // IOMUXC_SW_PAD_CTL_PAD_DRAM_ADDR04 (SDQS2_B_TRIM=01, SDQS2_TRIM=10)
setmem /32 0x020e0540 = 0x00018200 // IOMUXC_SW_PAD_CTL_PAD_DRAM_ADDR05 (SDQS3_B_TRIM=01, SDQS3_TRIM=10)
setmem /32 0x020e0544 = 0x00018200 // IOMUXC_SW_PAD_CTL_PAD_DRAM_ADDR06 (SDQS4_B_TRIM=01, SDQS4_TRIM=10)
setmem /32 0x020e0548 = 0x00018200 // IOMUXC_SW_PAD_CTL_PAD_DRAM_ADDR07 (SDQS5_B_TRIM=01, SDQS5_TRIM=10)
setmem /32 0x020e054C = 0x00018200 // IOMUXC_SW_PAD_CTL_PAD_DRAM_ADDR08 (SDQS6_B_TRIM=01, SDQS6_TRIM=10)
setmem /32 0x020e0550 = 0x00018200 // IOMUXC_SW_PAD_CTL_PAD_DRAM_ADDR09 (SDQS7_B_TRIM=01, SDQS7_TRIM=10)
setmem /32 0x021b08c0 = 0x24912489 // fine tune SDCLK duty cyc to low - seen to improve measured duty cycle of i.mx6
setmem /32 0x021b48c0 = 0x24914452
setmem /32 0x021b0018 = 0x00011740 // MMDC0_MDMISC, RALAT=0x5, WALAT=0x1
Test:
Passed stress memtester on one board.
Signed-off-by: Ye Li <ye.li@nxp.com>
(cherry picked from commit b7f43f47a78c9d0c14fe104daf22efab13709ab1)
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Need to configure the phy AR8031 to output 125Mhz clock for ENET
reference clock. And introduce a TX clock delay.
Signed-off-by: Ye Li <ye.li@nxp.com>
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Set the ID pin pad to pull up not the pull down at default, otherwise
we can't enter the device mode, but always detect as host.
After this change we have to use portA cable to play as host,
and use portB cable for device.
Signed-off-by: Ye.Li <B37916@freescale.com>
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Add board level support for android fastboot feature. Each board has
a android specified header file for defining android related configuraitons.
And add build targets for their android uboot images building.
For mx6qsabreauto, mx6sabresd and mx7dsabresd, we enable the android
fastboot exclusive with DFU.
Signed-off-by: Ye Li <ye.li@nxp.com>
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Port LDO bypass support from v2015 to support the features:
1. Add check for 1.2GHz core speed. If Speed grading fuse is for 1.2GHz,
enable LDO bypass and setup PMIC voltages. LDO bypass is dependent
on the flatten device tree file.
2. We set WDOG_B in set_anatop_bypass() before, because it is the only case, but now
on i.mx6sabreauto board, we didn't use ldo-bypass mode, but have to use WDOG_B to
reboot whole board, so split these code to independent function so that board file
can call it freely.
Signed-off-by: Ye Li <ye.li@nxp.com>
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Align board code and header file with imx_v2015.04.
Update pmic settings.
wrap spi code together using CONFIG_MXC_SPI macro.
To i.MX6SOLO, need to define CONFIG_MX6DL.
Signed-off-by: Peng Fan <peng.fan@nxp.com>
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Align ddr script with imx_v2015.04 latest ddr script.
mx6qp.cfg is 1.13 version
http://sw-stash.freescale.net/projects/IMX/repos/ddr-scripts-rel/commits/8111e4d0cd81226899be637013048281e3c097b4
http://compass.freescale.net/livelink/livelink?func=ll&objId=234753630&objAction=browse&viewType=1
arik_r2_sabre_ddr3_528_1.13.inc is for sabre-AI
arik_r2_sdb_ddr3_528_1.13.inc is for sabresd
Signed-off-by: Peng Fan <peng.fan@nxp.com>
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Add plugin.S for plugin boot initialization on mx6dq/dl/dqp sabresd board
and sabreauto board.
Need to enable "CONFIG_USE_PLUGIN" for this feature.
Signed-off-by: Ye Li <ye.li@nxp.com>
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Dynamic setting mmcdev and mmcroot for mx6sabresd and mx6qsabreauto.
Signed-off-by: Peng Fan <peng.fan@nxp.com>
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Support epdc for mx6dlsabresd board.
Introduce a new configuration file mx6dlsabresd_epdc_defconfig.
Add related settings.
Signed-off-by: Peng Fan <peng.fan@nxp.com>
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As the HDMI splash screen feature is not well supported,
we should not set it to be the default display. In case,
users leave the 'panel' uboot environment variable empty
and connect the board with a HDMI monitor, the HDMI detect
funtion will work and enable the HDMI splash screen. So,
this patch disables HDMI detect function so that users
may only explicitly set the 'panel' variable to be 'HDMI'
to use HDMI splash screen.
Signed-off-by: Peng Fan <Peng.Fan@freescale.com>
Signed-off-by: Liu Ying <Ying.Liu@freescale.com>
Signed-off-by: Ye.Li <B37916@freescale.com>
(cherry picked from commit d482c54a9fbf458fdb2270cf990d8ec727823bb1)
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-Change HDMI video mode to VGA.
-Add pixel clock fraction part setting in IPU driver,
fix video mode timing issue.
-Add overflow state clear workaround,
fix kernel hang in HDMI driver issue.
-Correct IPU clock to 264MHz.
Signed-off-by: Sandor Yu <R01008@freescale.com>
Signed-off-by: Nitin Garg <nitin.garg@freescale.com>
Signed-off-by: Peng Fan <Peng.Fan@freescale.com>
Signed-off-by: Ye Li <ye.li@nxp.com>
(cherry picked from commit 5028519b434d5dfbe53c48ac4b115ff8b69bbac7)
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Correct spelling of "U-Boot" shall be used in all written text
(documentation, comments in source files etc.).
Signed-off-by: Bin Meng <bmeng.cn@gmail.com>
Reviewed-by: Heiko Schocher <hs@denx.de>
Reviewed-by: Simon Glass <sjg@chromium.org>
Reviewed-by: Minkyu Kang <mk7.kang@samsung.com>
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Implement board_mmc_get_env_dev for the boards.
Following is examples:
SD1/SD2/SD3: return devno;
SD2/SD3: return devno - 1;
SD2/SD4: if (devno == 2), return dev - 2; return dev - 1;
Signed-off-by: Peng Fan <peng.fan@nxp.com>
Cc: Stefano Babic <sbabic@denx.de>
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The BOOTCFG value used by bmode for SABRESD eMMC boot are actually for SD card.
Fixed the value to correct one.
Signed-off-by: Ye Li <ye.li@nxp.com>
Signed-off-by: Peng Fan <peng.fan@nxp.com>
Reviewed-by: Stefano Babic <sbabic@denx.de>
Cc: Fabio Estevam <fabio.estevam@nxp.com>
Acked-by: Fabio Estevam <fabio.estevam@nxp.com>
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Update my email address to the NXP account.
Signed-off-by: Fabio Estevam <fabio.estevam@nxp.com>
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As per the AR8031 datasheet:
"For a reliable power on reset, suggest to keep asserting the reset
low long enough (10ms) to ensure the clock is stable and clock-to-reset
1ms requirement is satisfied."
So do as suggested and also add a 100us delay after deasserting the
reset line to guarantee that the PHY ID can be read correctly and the
Atheros 8031 PHY driver can be loaded automatically.
This results in a simpler code.
Signed-off-by: Fabio Estevam <fabio.estevam@nxp.com>
Acked-by: Joe Hershberger <joe.hershberger@ni.com>
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There is really no need to provide an empty reset_cpu() implementation,
so just remove it.
Signed-off-by: Fabio Estevam <fabio.estevam@freescale.com>
Reviewed-by: Stefano Babic <sbabic@denx.de>
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Add i.MX6DQP-Sabresd board support:
1. set fdt_file according to board_rev which is set at runtime.
2. Add mx6dqp_ddr_ioregs and calibration value for this board.
Signed-off-by: Peng Fan <Peng.Fan@freescale.com>
Cc: Stefano Babic <sbabic@denx.de>
Cc: Fabio Estevam <fabio.estevam@freescale.com>
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Remove duplicated SYS_SOC Kconfig entry from board Kconfig,
because we have this entry in arch/arm/cpu/armv7/mx6/Kconfig.
Signed-off-by: Peng Fan <Peng.Fan@freescale.com>
Cc: Stefano Babic <sbabic@denx.de>
Cc: Heiko Schocher <hs@denx.de>
Cc: Christian Gmeiner <christian.gmeiner@gmail.com>
Cc: Stefan Roese <sr@denx.de>
Cc: Troy Kisky <troy.kisky@boundarydevices.com>
Cc: Nikita Kiryanov <nikita@compulab.co.il>
Cc: "Eric Bénard" <eric@eukrea.com>
Cc: Fabio Estevam <fabio.estevam@freescale.com>
Cc: Tim Harvey <tharvey@gateworks.com>
Cc: Marek Vasut <marex@denx.de>
Cc: Markus Niebel <Markus.Niebel@tq-group.com>
Cc: Otavio Salvador <otavio@ossystems.com.br>
Acked-by: Stefan Roese <sr@denx.de>
Acked-by: Marek Vasut <marex@denx.de>
Acked-by: Christian Gmeiner <christian.gmeiner@gmail.com>
Acked-by: Markus Niebel <Markus.Niebel@tq-group.com>
Acked-by: Troy Kisky <troy.kisky@boundarydevices.com>
Acked-by: Igor Grinberg <grinberg@compulab.co.il>
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To i.MX6, DDR3 and LPDDR2 is supported, so rename function mx6_dram_cfg
to mx6_ddr3_cfg and the original mx6_dram_cfg function only is a wrapper.
The new reimplemented function mx6_dram_cfg only invokes mx6_ddr3_cfg
when ddr_type is for DDR3. Later we can use ddr_type to initialize
MMDC for LPDDR2.
Initialize ddr_type for different boards which enable SPL.
Signed-off-by: Peng Fan <Peng.Fan@freescale.com>
Cc: Stefano Babic <sbabic@denx.de>
Cc: Tim Harvey <tharvey@gateworks.com>
Cc: Stefan Roese <sr@denx.de>
Cc: Fabio Estevam <fabio.estevam@freescale.com>
Reviewed-by: Stefan Roese <sr@denx.de>
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Detect the SOC and board variant at runtime and change the dtb name,
but not hardcoding the fdt_file env variable.
Take the following patch as a reference.
Íd58699b157df75f1aa0b363ea9c21add21a0c
"mx6cuboxi: Load the correct 'fdtfile' variable"
Signed-off-by: Peng Fan <Peng.Fan@freescale.com>
Reviewed-by: Fabio Estevam <fabio.estevam@freescale.com>
Acked-by: Stefano Babic <sbabic@denx.de>
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The variable 'ret' is used to store the value returned by pfuze_mode_init(),
so it should of type 'int' instead of 'unsigned int' in order to correctly
handle negative numbers.
Fix the variable type.
Signed-off-by: Fabio Estevam <fabio.estevam@freescale.com>
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RTT_NOM_120OHM is not defined, so remove its ifdef.
Signed-off-by: Fabio Estevam <fabio.estevam@freescale.com>
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mx6sabresd has four MT41K128M16JT-125 chips. Each memory has 16-bit bus
and 2GiB, so fix the width and density fields accordingly.
Signed-off-by: Fabio Estevam <fabio.estevam@freescale.com>
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To normal mode, use APS switching mode.
To standy mode, use PFM switching mode.
Signed-off-by: Peng Fan <Peng.Fan@freescale.com>
Acked-by: Przemyslaw Marczak <p.marczak@samsung.com>
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Add pinmux settings, implement board_ehci_hcd_init and board_ehci_power
Signed-off-by: Peng Fan <Peng.Fan@freescale.com>
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Modify the pfuze init for mx6sabresd to use the shared
"pfuze_common_init" function. And move this initialization to
power_init_board.
Signed-off-by: Ye.Li <B37916@freescale.com>
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In U-boot it is preferred to access the register via structure pointer, so
convert it such style.
Signed-off-by: Fabio Estevam <fabio.estevam@freescale.com>
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Let's add mx6sabresd_spl_defconfig entry into MAINTAINERS, so that we avoid
getting a warning that the mx6sabresd_spl is not maintained.
Signed-off-by: Fabio Estevam <fabio.estevam@freescale.com>
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Make clear that current SPL code only supports the mx6q variant.
Signed-off-by: Fabio Estevam <fabio.estevam@freescale.com>
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Many boards use a minimal .cfg file in the SPL case.
Introduce spl_sd.cfg so that we can reuse it.
Signed-off-by: Fabio Estevam <fabio.estevam@freescale.com>
Acked-by: Stefano Babic <sbabic@denx.de>
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mx6sabresd_spl.cfg configures CCM registers, GPR registers and CCM_CCOSR.
Move the configuration to the spl code.
CCM_CCOSR setting is no longer required to get audio functionality in the
kernel, so remove such setting.
Signed-off-by: Fabio Estevam <fabio.estevam@freescale.com>
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Annotate 'static' when appropriate for the variables used locally.
Signed-off-by: Fabio Estevam <fabio.estevam@freescale.com>
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When an invalid USDHC port is passed we should return -EINVAL instead of 0.
Also, return the error immediately on fsl_esdhc_initialize() failure.
Signed-off-by: Fabio Estevam <fabio.estevam@freescale.com>
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This patch will enable the support for SPL on iMX6 SabreSD.
It tested on SD2 and SD3 mmc port (Switch 1 or 2 of SW6)
Signed-off-by: John Tobias <john.tobias.ph@gmail.com>
Acked-by: Stefano Babic <sbabic@denx.de>
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It's a trim version of mx6q_4x_mt41j128.cfg. It just removed
the related settings for DDR
Signed-off-by: John Tobias <john.tobias.ph@gmail.com>
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Add support for the 4.3'' Seiko WVGA parallel display.
In order to direct the splash screen to the Seiko display:
=> setenv panel SEIKO-WVGA
=> save
=> reset
Signed-off-by: Fabio Estevam <fabio.estevam@freescale.com>
Acked-by: Stefano Babic <sbabic@denx.de>
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This commit introduces a Kconfig symbol for each ARM CPU:
CPU_ARM720T, CPU_ARM920T, CPU_ARM926EJS, CPU_ARM946ES, CPU_ARM1136,
CPU_ARM1176, CPU_V7, CPU_PXA, CPU_SA1100.
Also, it adds the CPU feature Kconfig symbol HAS_VBAR which is selected
for CPU_ARM1176 and CPU_V7.
For each target, the corresponding CPU is selected and the definition of
SYS_CPU in the corresponding Kconfig file is removed.
Also, it removes redundant "string" type in some Kconfig files.
Signed-off-by: Georges Savoundararadj <savoundg@gmail.com>
Acked-by: Albert ARIBAUD <albert.u.boot@aribaud.net>
Cc: Masahiro Yamada <yamada.m@jp.panasonic.com>
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The single file conflict below is actually trivial.
Conflicts:
board/boundary/nitrogen6x/nitrogen6x.c
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Provide cgtqmx6eval board its own variant of ddr
setup config file. Move board/freescale/imx/ddr/
mx6q_4x_mt41j128.cfg to board/freescale/mx6sabresd/
as this is was designed for the mx6sabresd board.
Signed-off-by: Nitin Garg <nitin.garg@freescale.com>
Acked-by: Stefano Babic <sbabic@denx.de>
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MXC SPI driver has a feature whereas a GPIO line can be used to force CS high
across multiple transactions. This is set up by embedding the GPIO information
in the CS value:
cs = (cs | gpio << 8)
This merge of cs and gpio data into one value breaks the sf probe command:
if the use of gpio is required, invoking "sf probe <cs>" will not work, because
the CS argument doesn't have the GPIO information in it. Instead, the user must
use "sf probe <cs | gpio << 8>". For example, if bank 2 gpio 30 is used to force
cs high on cs 0, bus 0, then instead of typing "sf probe 0" the user now must
type "sf probe 15872".
This is inconsistent with the description of the sf probe command, and forces
the user to be aware of implementaiton details.
Fix this by introducing a new board function: board_spi_cs_gpio(), which will
accept a naked CS value, and provide the driver with the relevant GPIO, if one
is necessary.
Cc: Eric Nelson <eric.nelson@boundarydevices.com>
Cc: Eric Benard <eric@eukrea.com>
Cc: Fabio Estevam <fabio.estevam@freescale.com>
Cc: Tim Harvey <tharvey@gateworks.com>
Cc: Stefano Babic <sbabic@denx.de>
Cc: Tom Rini <trini@ti.com>
Cc: Marek Vasut <marex@denx.de>
Reviewed-by: Marek Vasut <marex@denx.de>
Signed-off-by: Nikita Kiryanov <nikita@compulab.co.il>
Reviewed-by: Jagannadha Sutradharudu Teki <jaganna@xilinx.com>
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Currently mx6dlsabresd shares the same DCD settings with the nitrogen board.
Provide a DCD configuration file specific to mx6dlsabresd with the settings
recommended by the Freescale hardware team.
Signed-off-by: Fabio Estevam <fabio.estevam@freescale.com>
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Now the types of CONFIG_SYS_{ARCH, CPU, SOC, VENDOR, BOARD, CONFIG_NAME}
are specified in arch/Kconfig.
We can delete the ones in arch and board Kconfig files.
This commit can be easily reproduced by the following command:
find . -name Kconfig -a ! -path ./arch/Kconfig | xargs sed -i -e '
/config[[:space:]]SYS_\(ARCH\|CPU\|SOC\|\VENDOR\|BOARD\|CONFIG_NAME\)/ {
N
s/\n[[:space:]]*string//
}
'
Signed-off-by: Masahiro Yamada <yamada.m@jp.panasonic.com>
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