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| author | John Tobias <john.tobias.ph@gmail.com> | 2014-11-12 14:27:42 -0800 |
|---|---|---|
| committer | Stefano Babic <sbabic@denx.de> | 2014-11-13 16:23:55 +0100 |
| commit | 340d1d3a0e645c515eb620751158c78f6327aca9 (patch) | |
| tree | 885a7a6691eb02ee8993c2fbc3e073707b0b04a4 /board/freescale/mx6sabresd | |
| parent | 988529745efb0f675edf07c5459fa673bdfbfa9d (diff) | |
| download | u-boot-imx-340d1d3a0e645c515eb620751158c78f6327aca9.zip u-boot-imx-340d1d3a0e645c515eb620751158c78f6327aca9.tar.gz u-boot-imx-340d1d3a0e645c515eb620751158c78f6327aca9.tar.bz2 | |
imx6: add data configuration file for SPL
It's a trim version of mx6q_4x_mt41j128.cfg. It just removed
the related settings for DDR
Signed-off-by: John Tobias <john.tobias.ph@gmail.com>
Diffstat (limited to 'board/freescale/mx6sabresd')
| -rw-r--r-- | board/freescale/mx6sabresd/mx6sabresd_spl.cfg | 58 |
1 files changed, 58 insertions, 0 deletions
diff --git a/board/freescale/mx6sabresd/mx6sabresd_spl.cfg b/board/freescale/mx6sabresd/mx6sabresd_spl.cfg new file mode 100644 index 0000000..2bf4817 --- /dev/null +++ b/board/freescale/mx6sabresd/mx6sabresd_spl.cfg @@ -0,0 +1,58 @@ +/* + * Copyright (C) 2011 Freescale Semiconductor, Inc. + * Jason Liu <r64343@freescale.com> + * + * SPDX-License-Identifier: GPL-2.0+ + * + * Refer doc/README.imximage for more details about how-to configure + * and create imximage boot image + * + * The syntax is taken as close as possible with the kwbimage + */ + +/* image version */ +IMAGE_VERSION 2 + +/* + * Boot Device : one of + * spi, sd (the board has no nand neither onenand) + */ +BOOT_FROM sd + +/* + * Device Configuration Data (DCD) + * + * Each entry must have the format: + * Addr-type Address Value + * + * where: + * Addr-type register length (1,2 or 4 bytes) + * Address absolute address of the register + * value value to be stored in the register + */ + +/* set the default clock gate to save power */ +DATA 4 0x020c4068 0x00C03F3F +DATA 4 0x020c406c 0x0030FC03 +DATA 4 0x020c4070 0x0FFFC000 +DATA 4 0x020c4074 0x3FF00000 +DATA 4 0x020c4078 0x00FFF300 +DATA 4 0x020c407c 0x0F0000C3 +DATA 4 0x020c4080 0x000003FF + +/* enable AXI cache for VDOA/VPU/IPU */ +DATA 4 0x020e0010 0xF00000CF +/* set IPU AXI-id0 Qos=0xf(bypass) AXI-id1 Qos=0x7 */ +DATA 4 0x020e0018 0x007F007F +DATA 4 0x020e001c 0x007F007F + +/* + * Setup CCM_CCOSR register as follows: + * + * cko1_en = 1 --> CKO1 enabled + * cko1_div = 111 --> divide by 8 + * cko1_sel = 1011 --> ahb_clk_root + * + * This sets CKO1 at ahb_clk_root/8 = 132/8 = 16.5 MHz + */ +DATA 4 0x020c4060 0x000000fb |