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* ENGR00155133: Add sata support for imx6Terry Lv2011-08-22-0/+64
| | | | | | Init clocks, phy and pll for sata. Signed-off-by: Terry Lv <r65388@freescale.com>
* ENGR00155156 [MX6]Clean up debug info in ubootAnson Huang2011-08-22-1/+0
| | | | | | | | 1. ENET don't need to enable ENET pll clock; 2. Enable cpu debug clock in case of using JTAG; 3. Clean up some debug info during bring up. Signed-off-by: Anson Huang <b20788@freescale.com>
* ENGR00152755 MX6 Switch DRAM init script from plugin to DCD for emmc fastbootAnish Trivedi2011-07-06-1/+1
| | | | | | | | | | | | | | | | | ROM requires DCD table instead of plugin to initialize DRAM if emmc fastboot mode is to be used. Therefore, switched the DRAM script from plugin to DCD table. The DCD table created is based on the following RVD script: Arik_init_DDR3_528MHz_002.inc found at http://compass.freescale.net/livelink/livelink?func=ll&objId=222928845 When fastboot mode is used by ROM, the MMC_BOOT register of USDHC does not get reset when RSTA bit is set by uboot driver. Therefore, need to write 0 to it manually during driver init. This brings USDHC out of fastboot mode, allowing normal communication with emmc to proceed in uboot. Changed comments for DLL delay to be more accurate. Signed-off-by: Anish Trivedi <anish@freescale.com>
* ENGR00139206 MX6 USDHC eMMC 4.4 supportAnish Trivedi2011-07-05-4/+17
| | | | | | | | | | | New bit definitions in USDHC. Added is_usdhc variable to fsl_esdhc_cfg to distinguish between ESDHC and USDHC. Enabled DDR mode support in USDHC. Created a config to customize target delay for DDR mode. Modified USDHC pad settings to make DDR mode work for all emmcs at 50 MHz. Signed-off-by: Anish Trivedi <anish@freescale.com>
* ENGR00139198: iMX61 uBoot add ENET supportZeng Zhaoming2011-06-27-1/+3
| | | | | | | | | | | | | | | | Add ENET and AR8031 PHY support to uboot. To make it works on sabreauto, need do following changes: 1. rework phy to output 125M clock from CLK_25M signal, and the 125M clock input to SoC as reference clock to generate RGMII_TXC clock. 2. Enable TXC delay in PHY debug register. 3. set ENET working in RMII mode. 4. set ENET working at 1000M or 100M/10M. 5. set ENET TX fifo to maximum to avoid underrun error. 6. force AR8031 PHY working at 100M Signed-off-by: Anson Huang <b20788@freescale.com> Signed-off-by: Zeng Zhaoming <b32542@freescale.com>
* ENGR00144424 MX6: enable uboot for ARM2(SABREAUTO) CPU boardAnson Huang2011-06-24-0/+437
Use 528M DDR script Disable L2 cache because rom enable L2 cache when use plug-in Fix usdhc pad settings Remove mac address hardcode Signed-off-by: Anson Huang <b20788@freescale.com> Signed-off-by: Richard Zhu <r65037@freescale.com> Signed-off-by: Terry Lv <r65388@freescale.com> Signed-off-by: Anish Trivedi <anish@freescale.com> Signed-off-by: Jason Liu <r64343@freescale.com>