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| author | Anish Trivedi <anish@freescale.com> | 2011-06-22 17:49:45 -0500 |
|---|---|---|
| committer | Anish Trivedi <anish@freescale.com> | 2011-07-05 14:28:09 -0500 |
| commit | 82102d3fdeae0dcd79d9b3ab7daa96bebd5ad290 (patch) | |
| tree | a21029195468b8d1ffcc134d8bb25fb6e724eb90 /board/freescale/mx6q_sabreauto/mx6q_sabreauto.c | |
| parent | c2ee955784881a2f3ac4c0cc234ba23d83205cb1 (diff) | |
| download | u-boot-imx-82102d3fdeae0dcd79d9b3ab7daa96bebd5ad290.zip u-boot-imx-82102d3fdeae0dcd79d9b3ab7daa96bebd5ad290.tar.gz u-boot-imx-82102d3fdeae0dcd79d9b3ab7daa96bebd5ad290.tar.bz2 | |
ENGR00139206 MX6 USDHC eMMC 4.4 support
New bit definitions in USDHC.
Added is_usdhc variable to fsl_esdhc_cfg to distinguish between ESDHC
and USDHC.
Enabled DDR mode support in USDHC.
Created a config to customize target delay for DDR mode.
Modified USDHC pad settings to make DDR mode work for all emmcs at 50 MHz.
Signed-off-by: Anish Trivedi <anish@freescale.com>
Diffstat (limited to 'board/freescale/mx6q_sabreauto/mx6q_sabreauto.c')
| -rw-r--r-- | board/freescale/mx6q_sabreauto/mx6q_sabreauto.c | 21 |
1 files changed, 17 insertions, 4 deletions
diff --git a/board/freescale/mx6q_sabreauto/mx6q_sabreauto.c b/board/freescale/mx6q_sabreauto/mx6q_sabreauto.c index 135dff0..3190997 100644 --- a/board/freescale/mx6q_sabreauto/mx6q_sabreauto.c +++ b/board/freescale/mx6q_sabreauto/mx6q_sabreauto.c @@ -200,10 +200,10 @@ int board_eth_init(bd_t *bis) #ifdef CONFIG_CMD_MMC struct fsl_esdhc_cfg usdhc_cfg[4] = { - {USDHC1_BASE_ADDR, 1, 1}, - {USDHC2_BASE_ADDR, 1, 1}, - {USDHC3_BASE_ADDR, 1, 1}, - {USDHC4_BASE_ADDR, 1, 1}, + {USDHC1_BASE_ADDR, 1, 1, 1}, + {USDHC2_BASE_ADDR, 1, 1, 1}, + {USDHC3_BASE_ADDR, 1, 1, 1}, + {USDHC4_BASE_ADDR, 1, 1, 1}, }; #ifdef CONFIG_DYNAMIC_MMC_DEVNO @@ -301,6 +301,19 @@ int board_mmc_init(bd_t *bis) return -1; } +/* For DDR mode operation, provide target delay parameter for each SD port. + * Use cfg->esdhc_base to distinguish the SD port #. The delay for each port + * is dependent on trace lengths for that particular port. If the following + * CONFIG is not defined, then the default target delay value will be used. + */ +#ifdef CONFIG_GET_DDR_TARGET_DELAY +u32 get_ddr_delay(struct fsl_esdhc *cfg) +{ + /* No delay required on SABRE Auto board SD ports */ + return 0; +} +#endif + #endif int board_init(void) |