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* imx6: icorem6_rqs: Add FEC supportJagan Teki2016-12-16-0/+1
| | | | | | | | | Add FEC support for Engicam i.CoreM6 RQS modules. Cc: Stefano Babic <sbabic@denx.de> Cc: Matteo Lisi <matteo.lisi@engicam.com> Cc: Michael Trimarchi <michael@amarulasolutions.com> Signed-off-by: Jagan Teki <jagan@amarulasolutions.com>
* arm: dts: imx6qdl-icore-rqs: Add FEC nodeJagan Teki2016-12-16-0/+46
| | | | | | | | | Add FEC node for Engicam i.CoreM6 RQS modules. Cc: Stefano Babic <sbabic@denx.de> Cc: Matteo Lisi <matteo.lisi@engicam.com> Cc: Michael Trimarchi <michael@amarulasolutions.com> Signed-off-by: Jagan Teki <jagan@amarulasolutions.com>
* imx6: geam6ul: Add FEC supportJagan Teki2016-12-16-0/+1
| | | | | | | | | Add FEC support for Engicam GEAM6UL module. Cc: Stefano Babic <sbabic@denx.de> Cc: Matteo Lisi <matteo.lisi@engicam.com> Cc: Michael Trimarchi <michael@amarulasolutions.com> Signed-off-by: Jagan Teki <jagan@amarulasolutions.com>
* arm: dts: imx6ul-geam: Add FEC nodeJagan Teki2016-12-16-0/+21
| | | | | | | | | Add FEC node for Engicam GEAM6UL module. Cc: Stefano Babic <sbabic@denx.de> Cc: Matteo Lisi <matteo.lisi@engicam.com> Cc: Michael Trimarchi <michael@amarulasolutions.com> Signed-off-by: Jagan Teki <jagan@amarulasolutions.com>
* imx6: icorem6_rqs: Add I2C supportJagan Teki2016-12-16-0/+1
| | | | | | | | | | | | | | | | | | | | | | | | | | | Add I2C support for Engicam i.CoreM6 RQS modules. icorem6qdl-rqs> i2c bus Bus 0: i2c@021a0000 Bus 1: i2c@021a4000 Bus 2: i2c@021a8000 icorem6qdl-rqs> i2c dev 0 Setting bus to 0 icorem6qdl-rqs> i2c speed 100000 Setting bus speed to 100000 Hz icorem6qdl-rqs> i2c probe Valid chip addresses: 4F icorem6qdl-rqs> i2c md 4F 0xff 00ff: ff ff ff ff ff ff ff ff ff ff ff ff ff ff ff ff ................ icorem6qdl-rqs> i2c bus Bus 0: i2c@021a0000 (active 0) 4f: generic_4f, offset len 1, flags 0 Bus 1: i2c@021a4000 Bus 2: i2c@021a8000 Cc: Stefano Babic <sbabic@denx.de> Cc: Matteo Lisi <matteo.lisi@engicam.com> Cc: Michael Trimarchi <michael@amarulasolutions.com> Signed-off-by: Jagan Teki <jagan@amarulasolutions.com>
* arm: dts: imx6qdl-icore-rqs: Add I2C node'sJagan Teki2016-12-16-0/+41
| | | | | | | | | Add I2C nodes for Engicam i.CoreM6 RQS modules. Cc: Stefano Babic <sbabic@denx.de> Cc: Matteo Lisi <matteo.lisi@engicam.com> Cc: Michael Trimarchi <michael@amarulasolutions.com> Signed-off-by: Jagan Teki <jagan@amarulasolutions.com>
* arm: imx6q: Add Engicam i.CoreM6 Solo/Duallite RQS Starter Kit initial supportJagan Teki2016-12-16-0/+51
| | | | | | | | | | | | | | | | | | | | | | | | | | | | | Boot from MMC: ------------- U-Boot SPL 2016.11-rc2-g217bd8e-dirty (Nov 08 2016 - 22:56:07) Trying to boot from MMC1 U-Boot 2016.11-rc2-g217bd8e-dirty (Nov 08 2016 - 22:56:07 +0530) CPU: Freescale i.MX6DL rev1.3 at 792 MHz Reset cause: POR Model: Engicam i.CoreM6 DualLite/Solo RQS Starter Kit DRAM: 512 MiB MMC: FSL_SDHC: 0 *** Warning - bad CRC, using default environment In: serial Out: serial Err: serial Net: CPU Net Initialization Failed No ethernet found. Hit any key to stop autoboot: 0 icorem6qdl-rqs> Cc: Stefano Babic <sbabic@denx.de> Cc: Matteo Lisi <matteo.lisi@engicam.com> Cc: Michael Trimarchi <michael@amarulasolutions.com> Signed-off-by: Jagan Teki <jagan@amarulasolutions.com>
* arm: imx6q: Add Engicam i.CoreM6 Quad/Dual RQS Starter Kit initial supportJagan Teki2016-12-16-0/+145
| | | | | | | | | | | | | | | | | | | | | | | | | | | | | Boot from MMC: ------------- U-Boot SPL 2016.11-rc2-g217bd8e-dirty (Nov 08 2016 - 22:59:44) Trying to boot from MMC1 U-Boot 2016.11-rc2-g217bd8e-dirty (Nov 08 2016 - 22:59:44 +0530) CPU: Freescale i.MX6D rev1.2 at 792 MHz Reset cause: POR Model: Engicam i.CoreM6 Quad/Dual RQS Starter Kit DRAM: 512 MiB MMC: FSL_SDHC: 0 *** Warning - bad CRC, using default environment In: serial Out: serial Err: serial Net: CPU Net Initialization Failed No ethernet found. Hit any key to stop autoboot: 0 icorem6qdl-rqs> Cc: Stefano Babic <sbabic@denx.de> Cc: Matteo Lisi <matteo.lisi@engicam.com> Cc: Michael Trimarchi <michael@amarulasolutions.com> Signed-off-by: Jagan Teki <jagan@amarulasolutions.com>
* imx6: geam6ul: Add I2C supportJagan Teki2016-12-16-0/+1
| | | | | | | | | | | | | | | | | | | | | | | Add I2C support for Engicam GEAM6UL module. geam6ul> i2c bus Bus 0: i2c@021a0000 Bus 1: i2c@021a4000 geam6ul> i2c dev 0 Setting bus to 0 geam6ul> i2c dev Current bus is 0 geam6ul> i2c speed 100000 Setting bus speed to 100000 Hz geam6ul> i2c probe Valid chip addresses: 2C geam6ul> i2c md 2C 0xff 00ff: 00 00 00 00 0f f0 01 64 ff ff 00 00 00 00 00 00 .......d........ Cc: Stefano Babic <sbabic@denx.de> Cc: Matteo Lisi <matteo.lisi@engicam.com> Cc: Michael Trimarchi <michael@amarulasolutions.com> Signed-off-by: Jagan Teki <jagan@amarulasolutions.com>
* arm: dts: imx6ul-geam: Add I2C nodesJagan Teki2016-12-16-0/+28
| | | | | | | | | Add I2C nodes for Engicam GEAM6UL module. Cc: Stefano Babic <sbabic@denx.de> Cc: Matteo Lisi <matteo.lisi@engicam.com> Cc: Michael Trimarchi <michael@amarulasolutions.com> Signed-off-by: Jagan Teki <jagan@amarulasolutions.com>
* arm: imx6ul: Add Engicam GEAM6UL Starter Kit initial supportJagan Teki2016-12-16-1/+132
| | | | | | | | | | | | | | | | | | | | | | | | | | | | | | Boot Log: -------- U-Boot SPL 2016.11-rc2-00144-g922adaa-dirty (Oct 28 2016 - 18:55:30) Trying to boot from MMC1 U-Boot 2016.11-rc2-00144-g922adaa-dirty (Oct 28 2016 - 18:55:30 +0530) CPU: Freescale i.MX6UL rev1.1 528 MHz (running at 396 MHz) CPU: Industrial temperature grade (-40C to 105C) at 43C Reset cause: POR Model: Engicam GEAM6UL DRAM: 128 MiB MMC: FSL_SDHC: 0 *** Warning - bad CRC, using default environment In: serial Out: serial Err: serial Net: CPU Net Initialization Failed No ethernet found. Hit any key to stop autoboot: 0 geam6ul> Cc: Stefano Babic <sbabic@denx.de> Cc: Matteo Lisi <matteo.lisi@engicam.com> Cc: Michael Trimarchi <michael@amarulasolutions.com> Signed-off-by: Jagan Teki <jagan@amarulasolutions.com>
* arm: dts: Add devicetree for i.MX6ULJagan Teki2016-12-16-0/+942
| | | | | | | | | | | | | Add i.MX6UL dtsi support from Linux. Here is the last commit: "ARM: dts: add gpio-ranges property to iMX GPIO controllers" (sha1: bb728d662bed0fe91b152550e640cb3f6caa972c) Cc: Stefano Babic <sbabic@denx.de> Cc: Matteo Lisi <matteo.lisi@engicam.com> Cc: Michael Trimarchi <michael@amarulasolutions.com> Signed-off-by: Jagan Teki <jagan@amarulasolutions.com>
* imx6: icorem6: Add I2C supportJagan Teki2016-12-16-0/+1
| | | | | | | | | | | | | | | | | | | | | | | | Add I2C support for Engicam i.CoreM6 qdl board. icorem6qdl> i2c bus Bus 0: i2c@021a0000 Bus 1: i2c@021a4000 Bus 2: i2c@021a8000 icorem6qdl> i2c dev 2 Setting bus to 2 icorem6qdl> i2c speed 100000 Setting bus speed to 100000 Hz icorem6qdl> i2c probe Valid chip addresses: 2C icorem6qdl> i2c md 2C 0xff 00ff: 00 00 00 00 0f f0 01 64 ff ff 00 00 00 00 00 00 .......d........ Cc: Stefano Babic <sbabic@denx.de> Cc: Heiko Schocher <hs@denx.de> Cc: Matteo Lisi <matteo.lisi@engicam.com> Cc: Michael Trimarchi <michael@amarulasolutions.com> Signed-off-by: Jagan Teki <jagan@amarulasolutions.com> Acked-by: Heiko Schocher <hs@denx.de>
* icorem6: Use CONFIG_DM_ETH supportJagan Teki2016-12-16-0/+1
| | | | | | | | | | | | Use CONFIG_DM_ETH and remove board_eth_init code from board files. Cc: Joe Hershberger <joe.hershberger@ni.com> Cc: Peng Fan <peng.fan@nxp.com> Cc: Stefano Babic <sbabic@denx.de> Cc: Michael Trimarchi <michael@amarulasolutions.com> Acked-by: Joe Hershberger <joe.hershberger@ni.com> Signed-off-by: Jagan Teki <jagan@amarulasolutions.com>
* ARM: dts: imx6qdl-icore: Add FEC supportJagan Teki2016-12-16-0/+24
| | | | | | | | | | Add FEC dts support for Engicam i.CoreM6 dql modules. Cc: Stefano Babic <sbabic@denx.de> Cc: Matteo Lisi <matteo.lisi@engicam.com> Cc: Michael Trimarchi <michael@amarulasolutions.com> Acked-by: Joe Hershberger <joe.hershberger@ni.com> Signed-off-by: Jagan Teki <jagan@amarulasolutions.com>
* arm: imx: add i.MX53 Beckhoff CX9020 Embedded PCPatrick Bruenn2016-12-16-0/+1499
| | | | | | | | | | | | | | | | Add CX9020 board based on mx53loco. Add simplified imx53 base device tree from kernel v4.8-rc8, to reuse serial_mxc with DTE and prepare for device tree migration of other functions and imx53 devices. The CX9020 differs from i.MX53 Quick Start Board by: - use uart2 instead of uart1 - DVI-D connector instead of VGA - no audio - CCAT FPGA connected to emi - enable rtc Signed-off-by: Patrick Bruenn <p.bruenn@beckhoff.com>
* arm: imx: add i.MX6SLL EVK board supportPeng Fan2016-12-16-0/+809
| | | | | | | | | | | | | | | | | | | | | | | | | | | | Add i.MX6SLL EVK board support. 1. Add imx6sll-evk device tree. 2. Enable SDHC/I2C/UART. 3. Enable REGULATOR/PMIC/I2C/GPIO/SDHC/PINCTRL driver. Boot Log: U-Boot 2016.11-00127-gc635871-dirty (Nov 24 2016 - 13:28:19 +0800) CPU: Freescale i.MX6SLL rev1.0 at 792MHz CPU: Commercial temperature grade (0C to 95C)Reset cause: POR Model: Freescale i.MX6SLL EVK Board Board: MX6SLL EVK DRAM: 2 GiB i2c bus 0 at 35258368, no gpio pinctrl state. PMIC: PFUZE100! DEV_ID=0x10 REV_ID=0x21 MMC: FSL_SDHC: 0, FSL_SDHC: 1, FSL_SDHC: 2 In: serial Out: serial Err: serial Net: CPU Net Initialization Failed No ethernet found. Hit any key to stop autoboot: 0 Signed-off-by: Peng Fan <peng.fan@nxp.com> Cc: Stefano Babic <sbabic@denx.de>
* arm: dts: add i.MX6SLL device treePeng Fan2016-12-16-0/+1741
| | | | | | | Add i.MX6SLL device tree. Signed-off-by: Peng Fan <peng.fan@nxp.com> Cc: Stefano Babic <sbabic@denx.de>
* imx-common: lcdif: update lcdif regs for i.MX6SL/SLLPeng Fan2016-12-16-3/+4
| | | | | | | Update lcdif regs for i.MX6SL/SLL Signed-off-by: Ye.Li <ye.li@nxp.com> Signed-off-by: Peng Fan <peng.fan@nxp.com>
* imx: mx6sll: add Kconfig entry for i.MX6SLLPeng Fan2016-12-16-0/+4
| | | | | | add Kconfig entry for i.MX6SLL Signed-off-by: Peng Fan <peng.fan@nxp.com>
* imx-common: cache: configure L2 Cache for i.MX6SLLPeng Fan2016-12-16-8/+9
| | | | | | | | If L2 cache configured as OCRAM, reset it. Switch to use runtime check. Signed-off-by: Peng Fan <peng.fan@nxp.com> Cc: Stefano Babic <sbabic@denx.de>
* imx: mx6sll: add clock supportPeng Fan2016-12-16-7/+21
| | | | | | | Add clock support for i.MX6SLL. Signed-off-by: Peng Fan <peng.fan@nxp.com> Cc: Stefano Babic <sbabic@denx.de>
* imx: clock: gate clk before changing pix clk muxPeng Fan2016-12-16-21/+31
| | | | | | | | | | | The LCDIF Pixel clock mux is not glitchless, so need to gate before changing mux. Also change enable_lcdif_clock prototype with a new input parameter to indicate disable or enable. Signed-off-by: Peng Fan <peng.fan@nxp.com> Cc: Stefano Babic <sbabic@denx.de>
* imx: mx6sl: add lcdif clock supportPeng Fan2016-12-16-19/+80
| | | | | | Add lcdif clock support for i.MX6SL. Signed-off-by: Peng Fan <peng.fan@nxp.com>
* imx: mx6: lcdif: gate clock before changing muxPeng Fan2016-12-16-0/+10
| | | | | | | | The mux for the lcd clock is not glitchless, so need to first gate the clock before changing the mux. Signed-off-by: Peng Fan <peng.fan@nxp.com> Cc: Stefano Babic <sbabic@denx.de>
* imx: mx6: fix mmdc ch0 clk for 6SLPeng Fan2016-12-16-0/+5
| | | | | | | | | | >From RM, per_periph2_clk_sel option3 is: "derive clock from 198MHz clock (divided 392MHz PLL2 PFD)." So fix it. Signed-off-by: Peng Fan <peng.fan@nxp.com> Cc: Stefano Babic <sbabic@denx.de>
* imx: mx6sll: add iomux settingsPeng Fan2016-12-16-5/+11
| | | | | | | | Add iomux settings for i.MX6 SLL Signed-off-by: Peng Fan <peng.fan@nxp.com> Signed-off-by: Ye.Li <ye.li@nxp.com> Cc: Stefano Babic <sbabic@denx.de>
* imx-common: timer: add i.MX6SLL supportPeng Fan2016-12-16-3/+7
| | | | | | | Add i.MX6 SLL GPT timer support. Signed-off-by: Peng Fan <peng.fan@nxp.com> Cc: Stefano Babic <sbabic@denx.de>
* imx: mx6sll: update register addressPeng Fan2016-12-16-27/+50
| | | | | | | Update register address for i.MX6 SLL Signed-off-by: Peng Fan <peng.fan@nxp.com> Cc: Stefano Babic <sbabic@denx.de>
* imx: mx6sll: add pinmux header filesPeng Fan2016-12-16-0/+1021
| | | | | | | Add i.MX6SLL pinmux header files Signed-off-by: Peng Fan <peng.fan@nxp.com> Cc: Stefano Babic <sbabic@denx.de>
* imx: add i.MX 6SLL CPU typePeng Fan2016-12-16-1/+5
| | | | | | | | Add i.MX6SLL cpu type. MXC_CPU_MX6D is not a real value in chip, so change it to 0x6A. Signed-off-by: Peng Fan <peng.fan@nxp.com> Cc: Stefano Babic <sbabic@denx.de>
* board/liteboard: Add support for liteBoardMarcin Niestroj2016-12-16-0/+5
| | | | | | | | | | | | liteBoard is a development board which uses liteSOM as its base. Hardware specification: * liteSOM (i.MX6UL, DRAM, eMMC) * Ethernet PHY (id 0) * USB host (usb_otg1) * MicroSD slot (uSDHC1) Signed-off-by: Marcin Niestroj <m.niestroj@grinn-global.com>
* ARM: imx6ul: Add support for liteSOMMarcin Niestroj2016-12-16-0/+231
| | | | | | | | | | | | | | | | liteSOM is a System On Module (http://grinn-global.com/litesom/). It can't exists on its own, but will be used as part of other boards. Hardware specification: * NXP i.MX6UL processor * 256M or 512M DDR3 memory * optional eMMC (uSDHC2) Here we treat SOM similar to SOC, so we place it inside arch/arm/mach-* directory and make it possible to reuse initialization code (i.e. DDR, eMMC init) for all boards that use it. Signed-off-by: Marcin Niestroj <m.niestroj@grinn-global.com>
* udoo_neo: Add thermal supportBreno Lima2016-12-16-0/+2
| | | | | | | Add thermal support on the Kconfig file. Signed-off-by: Breno Lima <breno.lima@nxp.com> Reviewed-by: Fabio Estevam <fabio.estevam@nxp.com>
* udoo_neo: Move MX6SX configuration to KconfigBreno Lima2016-12-16-0/+1
| | | | | | | | | It's not necessary to define the processor in the defconfig file. The preferred method to select the SoC is via Kconfig file. Signed-off-by: Breno Lima <breno.lima@nxp.com> Reviewed-by: Fabio Estevam <fabio.estevam@nxp.com>
* arm: imx: initial support for colibri imx6Max Krummenacher2016-12-16-0/+8
| | | | | | | | This adds board support for the Toradex module family Colibri iMX6. The familiy consists of a module with i.MX6 DualLite, i.MX6 Solo, both with a version for commercial and industrial temperature range. Signed-off-by: Max Krummenacher <max.krummenacher@toradex.com>
* arm: imx: initial support for apalis imx6Max Krummenacher2016-12-16-0/+8
| | | | | | | | This adds board support for the Toradex module family Apalis iMX6. The familiy consists of a module with i.MX6 Dual, i.MX6 Quad with commercial and industrial temperature range. Signed-off-by: Max Krummenacher <max.krummenacher@toradex.com>
* ARM: dts: vf: Fix warning about missing reg propertyStefan Agner2016-12-16-0/+2
| | | | | | | | | Add proper reg values for the two AIPS bus nodes. This avoids this two warnings: Node /soc/aips-bus@40000000 has a unit name, but no reg property Node /soc/aips-bus@40080000 has a unit name, but no reg property Signed-off-by: Stefan Agner <stefan.agner@toradex.com>
* Merge branch 'master' of git://git.denx.de/u-bootStefano Babic2016-12-16-1956/+3817
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| * Merge git://www.denx.de/git/u-boot-marvellTom Rini2016-12-12-64/+261
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| | * arm64: mvebu: Add L3 cache flush functionality to A8K familyKonstantin Porotchkin2016-12-12-0/+61
| | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | Add missing L3 cache flush functionality which absence prevents Linux kernel from normal boot in case the L3 cache is enabled by ATF. The L3 cache is named the "last level" cache in order to keep the terminology similar to the ATF code. This cache should not be disabled by u-boot since the Linux kernel cannot activate it, so it is activates at ATF stage. However the cache flush is required for preventing data corruption after disabling the MMU and the data cache before passing control to the loaded Linux image. Signed-off-by: Konstantin Porotchkin <kostap@marvell.com> Cc: Stefan Roese <sr@denx.de> Cc: Nadav Haklai <nadavh@marvell.com> Cc: Neta Zur Hershkovits <neta@marvell.com> Cc: Omri Itach <omrii@marvell.com> Cc: Igal Liberman <igall@marvell.com> Cc: Haim Boot <hayim@marvell.com> Cc: Hanna Hawa <hannah@marvell.com> Signed-off-by: Stefan Roese <sr@denx.de>
| | * arm64: mvebu: Add pin control nodes to A8K family DTS filesKonstantin Porotchkin2016-12-12-0/+161
| | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | Add pin control nodes to APN806, CP-master, CP-slave and Armada-7040 and Armada-8040 boards DTS files Signed-off-by: Konstantin Porotchkin <kostap@marvell.com> Cc: Stefan Roese <sr@denx.de> Cc: Nadav Haklai <nadavh@marvell.com> Cc: Neta Zur Hershkovits <neta@marvell.com> Cc: Omri Itach <omrii@marvell.com> Cc: Igal Liberman <igall@marvell.com> Cc: Haim Boot <hayim@marvell.com> Cc: Hanna Hawa <hannah@marvell.com> Signed-off-by: Stefan Roese <sr@denx.de>
| | * arm64: mvebu: pinctrl: Add pin control driver for A8K familyKonstantin Porotchkin2016-12-12-0/+17
| | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | Add a DM port of Marvell pin control driver. The A8K SoC family contains several silicone dies interconnected in a single package. Every die is normally equipped with its own pin controller unit. There are 2 pin controllers in A70x0 SoC and 3 in A80x0 SoC. Signed-off-by: Konstantin Porotchkin <kostap@marvell.com> Reviewed-by: Simon Glass <sjg@chromium.org> Cc: Simon Glass <sjg@chromium.org> Cc: Stefan Roese <sr@denx.de> Cc: Nadav Haklai <nadavh@marvell.com> Cc: Neta Zur Hershkovits <neta@marvell.com> Cc: Omri Itach <omrii@marvell.com> Cc: Igal Liberman <igall@marvell.com> Cc: Haim Boot <hayim@marvell.com> Cc: Hanna Hawa <hannah@marvell.com> Signed-off-by: Stefan Roese <sr@denx.de>
| | * arm64: mvebu: Modify the A8K SPI and I2C config in DTSKonstantin Porotchkin2016-12-12-67/+25
| | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | Align the Armada-8040-db and Armada-7040-db SPI and I2C DTS settings with latest DB settings: - 8040-db: disable i2c0 and spi0 on AP (MPPs are reserved for SDIO) - 8040-db: disable cps_i2c0 on CP1 - 8040-db: enable spi1 on CP1 (the new location of the boot flash) The spi1 on CP1 is aliased as spi0 since this is the way the driver enumerates it. Signed-off-by: Konstantin Porotchkin <kostap@marvell.com> Reviewed-by: Stefan Roese <sr@denx.de> Cc: Stefan Roese <sr@denx.de> Cc: Nadav Haklai <nadavh@marvell.com> Cc: Neta Zur Hershkovits <neta@marvell.com> Cc: Omri Itach <omrii@marvell.com> Cc: Igal Liberman <igall@marvell.com> Cc: Haim Boot <hayim@marvell.com> Cc: Hanna Hawa <hannah@marvell.com> Signed-off-by: Stefan Roese <sr@denx.de>
| * | Merge branch 'master' of git://git.denx.de/u-boot-uniphierTom Rini2016-12-12-1857/+2691
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| | * | ARM: uniphier: remove BLK selectMasahiro Yamada2016-12-11-1/+0
| | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | This is a user configurable option, but "select BLK" forces users to enable it. Even with this commit, BLK is still enabled by "default y if DM_MMC" for UniPhier SoCs; the difference is users can disable it if they do not need it. Signed-off-by: Masahiro Yamada <yamada.masahiro@socionext.com>
| | * | ARM: dts: uniphier: sync Device Tree with LinuxMasahiro Yamada2016-12-11-1851/+2684
| | | | | | | | | | | | | | | | | | | | | | | | Sync with the latest kernel. Signed-off-by: Masahiro Yamada <yamada.masahiro@socionext.com>
| | * | ARM: uniphier: remove unneeded parenthesesMasahiro Yamada2016-12-10-3/+3
| | | | | | | | | | | | | | | | | | | | | | | | Just a cosmetic cleanup. Signed-off-by: Masahiro Yamada <yamada.masahiro@socionext.com>
| | * | ARM: uniphier: remove unneeded initializerMasahiro Yamada2016-12-10-2/+4
| | |/ | | | | | | | | | | | | | | | This will be used to store the return value of readl(). Signed-off-by: Masahiro Yamada <yamada.masahiro@socionext.com>
| * | arm: am33xx: Initialize EMIF REG_PR_OLD_COUNT for BBB and am335x-evmJyri Sarha2016-12-09-0/+5
| | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | Initialize EMIF OCP_CONFIG registers REG_COS_COUNT_1, REG_COS_COUNT_2, and REG_PR_OLD_COUNT field for Beaglebone-Black and am335x-evm. With the default values LCDC suffers from DMA FIFO underflows and frame synchronization lost errors. The initialization values are the highest that work flawlessly when heavy memory load is generated by CPU. 32bpp colors were used in the test. On BBB the video mode used 110MHz pixel clock. The mode supported by the panel of am335x-evm uses 30MHz pixel clock. Signed-off-by: Jyri Sarha <jsarha@ti.com> Reviewed-by: Tom Rini <trini@konsulko.com>
generated by cgit v1.1 at 2024-07-05 00:44:55 +0000