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| author | Jyri Sarha <jsarha@ti.com> | 2016-12-09 12:29:13 +0200 |
|---|---|---|
| committer | Tom Rini <trini@konsulko.com> | 2016-12-09 15:00:03 -0500 |
| commit | 8c17cbdf8a8023abdd0009af4dc9dbc0541b4a0f (patch) | |
| tree | e6d601b384d2575eb5b3f1f8e91231a18835b39c /arch | |
| parent | 177f14da7f610ec26d3ab0aea2c8a75e2bfefa3a (diff) | |
| download | u-boot-imx-8c17cbdf8a8023abdd0009af4dc9dbc0541b4a0f.zip u-boot-imx-8c17cbdf8a8023abdd0009af4dc9dbc0541b4a0f.tar.gz u-boot-imx-8c17cbdf8a8023abdd0009af4dc9dbc0541b4a0f.tar.bz2 | |
arm: am33xx: Initialize EMIF REG_PR_OLD_COUNT for BBB and am335x-evm
Initialize EMIF OCP_CONFIG registers REG_COS_COUNT_1, REG_COS_COUNT_2,
and REG_PR_OLD_COUNT field for Beaglebone-Black and am335x-evm. With
the default values LCDC suffers from DMA FIFO underflows and frame
synchronization lost errors. The initialization values are the highest
that work flawlessly when heavy memory load is generated by CPU. 32bpp
colors were used in the test. On BBB the video mode used 110MHz pixel
clock. The mode supported by the panel of am335x-evm uses 30MHz pixel
clock.
Signed-off-by: Jyri Sarha <jsarha@ti.com>
Reviewed-by: Tom Rini <trini@konsulko.com>
Diffstat (limited to 'arch')
| -rw-r--r-- | arch/arm/include/asm/emif.h | 1 | ||||
| -rw-r--r-- | arch/arm/mach-omap2/am33xx/ddr.c | 4 |
2 files changed, 5 insertions, 0 deletions
diff --git a/arch/arm/include/asm/emif.h b/arch/arm/include/asm/emif.h index b00dece..9a46340 100644 --- a/arch/arm/include/asm/emif.h +++ b/arch/arm/include/asm/emif.h @@ -1171,6 +1171,7 @@ struct emif_regs { u32 sdram_tim1; u32 sdram_tim2; u32 sdram_tim3; + u32 ocp_config; u32 read_idle_ctrl; u32 zq_config; u32 temp_alert_config; diff --git a/arch/arm/mach-omap2/am33xx/ddr.c b/arch/arm/mach-omap2/am33xx/ddr.c index 6acf30c..690487e 100644 --- a/arch/arm/mach-omap2/am33xx/ddr.c +++ b/arch/arm/mach-omap2/am33xx/ddr.c @@ -180,6 +180,10 @@ void config_sdram(const struct emif_regs *regs, int nr) writel(regs->ref_ctrl, &emif_reg[nr]->emif_sdram_ref_ctrl); writel(regs->ref_ctrl, &emif_reg[nr]->emif_sdram_ref_ctrl_shdw); writel(regs->sdram_config, &emif_reg[nr]->emif_sdram_config); + + /* Write REG_COS_COUNT_1, REG_COS_COUNT_2, and REG_PR_OLD_COUNT. */ + if (regs->ocp_config) + writel(regs->ocp_config, &emif_reg[nr]->emif_l3_config); } /** |