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| author | Jagan Teki <jagan@amarulasolutions.com> | 2016-12-06 00:00:52 +0100 |
|---|---|---|
| committer | Stefano Babic <sbabic@denx.de> | 2016-12-16 17:15:27 +0100 |
| commit | 65613cada2be42392ec7b0d9be94d38b9a17ba9f (patch) | |
| tree | ab7bec9b44561db1683e04cf4321e35725c6f4ff /arch | |
| parent | 1ed2570f7eebd78b6ee698fa327a0d92a478d0bc (diff) | |
| download | u-boot-imx-65613cada2be42392ec7b0d9be94d38b9a17ba9f.zip u-boot-imx-65613cada2be42392ec7b0d9be94d38b9a17ba9f.tar.gz u-boot-imx-65613cada2be42392ec7b0d9be94d38b9a17ba9f.tar.bz2 | |
ARM: dts: imx6qdl-icore: Add FEC support
Add FEC dts support for Engicam i.CoreM6 dql modules.
Cc: Stefano Babic <sbabic@denx.de>
Cc: Matteo Lisi <matteo.lisi@engicam.com>
Cc: Michael Trimarchi <michael@amarulasolutions.com>
Acked-by: Joe Hershberger <joe.hershberger@ni.com>
Signed-off-by: Jagan Teki <jagan@amarulasolutions.com>
Diffstat (limited to 'arch')
| -rw-r--r-- | arch/arm/dts/imx6qdl-icore.dtsi | 24 |
1 files changed, 24 insertions, 0 deletions
diff --git a/arch/arm/dts/imx6qdl-icore.dtsi b/arch/arm/dts/imx6qdl-icore.dtsi index f424cd5..a485c3e 100644 --- a/arch/arm/dts/imx6qdl-icore.dtsi +++ b/arch/arm/dts/imx6qdl-icore.dtsi @@ -75,6 +75,14 @@ assigned-clock-parents = <&clks IMX6QDL_CLK_OSC>; }; +&fec { + pinctrl-names = "default"; + pinctrl-0 = <&pinctrl_enet>; + phy-reset-gpios = <&gpio7 12 GPIO_ACTIVE_LOW>; + phy-mode = "rmii"; + status = "okay"; +}; + &gpmi { pinctrl-names = "default"; pinctrl-0 = <&pinctrl_gpmi_nand>; @@ -118,6 +126,22 @@ }; &iomuxc { + pinctrl_enet: enetgrp { + fsl,pins = < + MX6QDL_PAD_ENET_CRS_DV__ENET_RX_EN 0x1b0b0 + MX6QDL_PAD_GPIO_16__ENET_REF_CLK 0x1b0b1 + MX6QDL_PAD_ENET_TX_EN__ENET_TX_EN 0x1b0b0 + MX6QDL_PAD_ENET_RXD1__ENET_RX_DATA1 0x1b0b0 + MX6QDL_PAD_ENET_RXD0__ENET_RX_DATA0 0x1b0b0 + MX6QDL_PAD_ENET_TXD1__ENET_TX_DATA1 0x1b0b0 + MX6QDL_PAD_ENET_TXD0__ENET_TX_DATA0 0x1b0b0 + MX6QDL_PAD_ENET_MDC__ENET_MDC 0x1b0b0 + MX6QDL_PAD_ENET_MDIO__ENET_MDIO 0x1b0b0 + MX6QDL_PAD_ENET_REF_CLK__GPIO1_IO23 0x1b0b0 + MX6QDL_PAD_GPIO_17__GPIO7_IO12 0x1b0b0 + >; + }; + pinctrl_flexcan1: flexcan1grp { fsl,pins = < MX6QDL_PAD_KEY_ROW2__FLEXCAN1_RX 0x1b020 |