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* x86: broadwell: Add a SATA driverSimon Glass2016-03-17-0/+270
* x86: broadwell: Add a pinctrl driverSimon Glass2016-03-17-0/+370
* x86: broadwell: Add a PCH driverSimon Glass2016-03-17-0/+839
* x86: Add basic support for broadwellSimon Glass2016-03-17-0/+1246
* x86: Add support for running Intel reference codeSimon Glass2016-03-17-0/+23
* x86: Drop all the old pin configuration codeSimon Glass2016-03-17-141/+0
* x86: Add an ICH6 pin configuration driverSimon Glass2016-03-17-0/+218
* x86: link: Add pin configuration to the device treeSimon Glass2016-03-17-0/+155
* x86: Update microcode for secondary CPUsSimon Glass2016-03-17-2/+12
* x86: ivybridge: Show microcode version for each coreSimon Glass2016-03-17-1/+2
* x86: Record the CPU details when starting each coreSimon Glass2016-03-17-1/+20
* x86: Move common MRC Kconfig options to the common fileSimon Glass2016-03-17-26/+62
* x86: Allow I/O functions to use pointersSimon Glass2016-03-17-2/+10
* x86: Add macros to clear and set I/O bitsSimon Glass2016-03-17-0/+22
* x86: ivybridge: Drop sandybridge_early_init()Simon Glass2016-03-17-2/+0
* x86: Move Intel Management Engine code to a common placeSimon Glass2016-03-17-369/+418
* x86: Rename PORT_RESET to IO_PORT_RESETSimon Glass2016-03-17-5/+5
* x86: Move common CPU code to its own placeSimon Glass2016-03-17-76/+162
* x86: Move common LPC code to its own placeSimon Glass2016-03-17-85/+166
* x86: Add the root-complex block to common intel registersSimon Glass2016-03-17-7/+9
* x86: Create a common header for Intel register accessSimon Glass2016-03-17-6/+22
* x86: Move microcode code to a common locationSimon Glass2016-03-17-4/+8
* x86: Move cache-as-RAM code into a common locationSimon Glass2016-03-17-1/+8
* x86: cpu: Add functions to return the family and steppingSimon Glass2016-03-17-0/+24
* x86: broadwell: Add a few microcode filesSimon Glass2016-03-17-0/+2272
* x86: Add comments to the SIPI vectorSimon Glass2016-03-17-0/+2
* x86: Tidy up mp_init to reduce duplicationSimon Glass2016-03-17-53/+26
* x86: Correct duplicate POST valuesSimon Glass2016-03-17-2/+2
* x86: gpio: Correct GPIO setup orderingSimon Glass2016-03-17-0/+5
* x86: dts: link: Add board ID GPIOsSimon Glass2016-03-17-0/+2
* x86: dts: link: Move SPD info into the memory controllerSimon Glass2016-03-17-111/+110
* x86: link: Add required GPIO propertiesSimon Glass2016-03-17-3/+9
* x86: Add some more common MSR indexesSimon Glass2016-03-17-20/+43
* x86: cpu: Make the vendor table constSimon Glass2016-03-17-1/+1
* x86: Support booting SeaBIOSBin Meng2016-03-17-0/+28
* x86: Implement functions for writing coreboot tableBin Meng2016-03-17-0/+147
* x86: Support writing configuration tables in high areaBin Meng2016-03-17-0/+11
* x86: Simplify codes in write_tables()Bin Meng2016-03-17-27/+34
* x86: Change write_acpi_tables() signature a little bitBin Meng2016-03-17-6/+5
* x86: Use a macro for ROM table alignmentBin Meng2016-03-17-5/+7
* x86: Change to use start/end address pair in write_tables()Bin Meng2016-03-17-6/+12
* x86: Clean up coreboot_tables.hBin Meng2016-03-17-73/+80
* x86: Move sysinfo related to sysinfo.hBin Meng2016-03-17-4/+2
* x86: Move asm/arch-coreboot/tables.h to a common placeBin Meng2016-03-17-3/+1
* dm: Use uclass_first_device_err() where it is usefulSimon Glass2016-03-14-20/+12
* x86: Add Intel Cougar Canyon 2 boardBin Meng2016-02-21-0/+109
* x86: ivybridge: bd82x6x: Support FSP enabled configurationBin Meng2016-02-21-1/+5
* x86: fsp: Make sure HOB list is not overwritten by U-BootBin Meng2016-02-21-0/+43
* x86: ivybridge: Add FSP supportBin Meng2016-02-21-0/+131
* x86: fix memalign() parameter orderStephen Warren2016-02-21-1/+1
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