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* arm: x86: Drop command-line code when CONFIG_CMDLINE is disabledSimon Glass2016-03-22-0/+4
* x86: Add congatec conga-QA3/E3845-4G (Bay Trail) supportStefan Roese2016-03-17-0/+283
* x86: Add support for the samus chromebookSimon Glass2016-03-17-0/+629
* x86: Support a chained-boot development flowSimon Glass2016-03-17-0/+80
* x86: dts: Drop memory SPD compatible stringSimon Glass2016-03-17-1/+0
* x86: ivybridge: Convert to use the common SDRAM codeSimon Glass2016-03-17-311/+83
* x86: Add common SDRAM-init codeSimon Glass2016-03-17-0/+327
* x86: Move common PCH code into a common placeSimon Glass2016-03-17-84/+99
* x86: Add a function to set the IOAPIC IDSimon Glass2016-03-17-0/+18
* x86: broadwell: Add support for high-speed I/O lane with MESimon Glass2016-03-17-0/+58
* x86: broadwell: Add support for SDRAM setupSimon Glass2016-03-17-0/+509
* x86: broadwell: Add power-control supportSimon Glass2016-03-17-0/+220
* x86: broadwell: Add reference code supportSimon Glass2016-03-17-0/+114
* x86: broadwell: Add an LPC driverSimon Glass2016-03-17-0/+110
* x86: broadwell: Add a northbridge driverSimon Glass2016-03-17-0/+60
* x86: broadwell: Add a SATA driverSimon Glass2016-03-17-0/+270
* x86: broadwell: Add a pinctrl driverSimon Glass2016-03-17-0/+370
* x86: broadwell: Add a PCH driverSimon Glass2016-03-17-0/+839
* x86: Add basic support for broadwellSimon Glass2016-03-17-0/+1246
* x86: Add support for running Intel reference codeSimon Glass2016-03-17-0/+23
* x86: Drop all the old pin configuration codeSimon Glass2016-03-17-141/+0
* x86: Add an ICH6 pin configuration driverSimon Glass2016-03-17-0/+218
* x86: link: Add pin configuration to the device treeSimon Glass2016-03-17-0/+155
* x86: Update microcode for secondary CPUsSimon Glass2016-03-17-2/+12
* x86: ivybridge: Show microcode version for each coreSimon Glass2016-03-17-1/+2
* x86: Record the CPU details when starting each coreSimon Glass2016-03-17-1/+20
* x86: Move common MRC Kconfig options to the common fileSimon Glass2016-03-17-26/+62
* x86: Allow I/O functions to use pointersSimon Glass2016-03-17-2/+10
* x86: Add macros to clear and set I/O bitsSimon Glass2016-03-17-0/+22
* x86: ivybridge: Drop sandybridge_early_init()Simon Glass2016-03-17-2/+0
* x86: Move Intel Management Engine code to a common placeSimon Glass2016-03-17-369/+418
* x86: Rename PORT_RESET to IO_PORT_RESETSimon Glass2016-03-17-5/+5
* x86: Move common CPU code to its own placeSimon Glass2016-03-17-76/+162
* x86: Move common LPC code to its own placeSimon Glass2016-03-17-85/+166
* x86: Add the root-complex block to common intel registersSimon Glass2016-03-17-7/+9
* x86: Create a common header for Intel register accessSimon Glass2016-03-17-6/+22
* x86: Move microcode code to a common locationSimon Glass2016-03-17-4/+8
* x86: Move cache-as-RAM code into a common locationSimon Glass2016-03-17-1/+8
* x86: cpu: Add functions to return the family and steppingSimon Glass2016-03-17-0/+24
* x86: broadwell: Add a few microcode filesSimon Glass2016-03-17-0/+2272
* x86: Add comments to the SIPI vectorSimon Glass2016-03-17-0/+2
* x86: Tidy up mp_init to reduce duplicationSimon Glass2016-03-17-53/+26
* x86: Correct duplicate POST valuesSimon Glass2016-03-17-2/+2
* x86: gpio: Correct GPIO setup orderingSimon Glass2016-03-17-0/+5
* x86: dts: link: Add board ID GPIOsSimon Glass2016-03-17-0/+2
* x86: dts: link: Move SPD info into the memory controllerSimon Glass2016-03-17-111/+110
* x86: link: Add required GPIO propertiesSimon Glass2016-03-17-3/+9
* x86: Add some more common MSR indexesSimon Glass2016-03-17-20/+43
* x86: cpu: Make the vendor table constSimon Glass2016-03-17-1/+1
* x86: Support booting SeaBIOSBin Meng2016-03-17-0/+28
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