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* x86: ich6_gpio: Convert to use proper DM APIBin Meng2016-02-05-153/+163
| | | | | | | | | | | | | | | | At present this GPIO driver still uses the legacy PCI API. Now that we have proper PCH drivers we can use those to obtain the information we need. While the device tree has nodes for the GPIO peripheral it is not in the right place. It should be on the PCI bus as a sub-peripheral of the PCH device. Update the device tree files to show the GPIO controller within the PCH, so that PCI access works as expected. This also adds '#address-cells' and '#size-cells' to the PCH node. Signed-off-by: Bin Meng <bmeng.cn@gmail.com> Reviewed-by: Simon Glass <sjg@chromium.org> Tested-by: Simon Glass <sjg@chromium.org>
* x86: pch: Implement get_gpio_base opBin Meng2016-02-05-0/+33
| | | | | | | | Implement get_gpio_base op for bd82x6x, pch7 and pch9 drivers. Signed-off-by: Bin Meng <bmeng.cn@gmail.com> Reviewed-by: Simon Glass <sjg@chromium.org> Tested-by: Simon Glass <sjg@chromium.org>
* dm: pch: Rename get_sbase op to get_spi_baseBin Meng2016-02-05-2/+2
| | | | | | | | Spell out 'sbase' to 'spi_base' so that it looks clearer. Signed-off-by: Bin Meng <bmeng.cn@gmail.com> Reviewed-by: Simon Glass <sjg@chromium.org> Tested-by: Simon Glass <sjg@chromium.org>
* dm: pch: Remove pch_get_version opBin Meng2016-02-05-6/+0
| | | | | | | | | | | | | pch_get_version op was only used by the ich spi controller driver, and does not really provide a good identification of pch controller so far, since we see plenty of Intel PCH chipsets and one differs from another a lot, which is not simply either a PCHV_7 or PCHV_9. Now that ich spi controller driver was updated to not get such info from pch, the pch_get_version op is useless now. Signed-off-by: Bin Meng <bmeng.cn@gmail.com> Reviewed-by: Simon Glass <sjg@chromium.org> Tested-by: Simon Glass <sjg@chromium.org>
* x86: quark: Drop unprotect_spi_flash()Bin Meng2016-02-05-17/+0
| | | | | | | | | Unprotecting SPI flash is now handled in the SPI controller driver, via a call to the PCH driver. Drop the ad-hoc version. Signed-off-by: Bin Meng <bmeng.cn@gmail.com> Reviewed-by: Simon Glass <sjg@chromium.org> Tested-by: Simon Glass <sjg@chromium.org>
* x86: tnc: Drop unprotect_spi_flash()Bin Meng2016-02-05-16/+0
| | | | | | | | | Unprotecting SPI flash is now handled in the SPI controller driver, via a call to the PCH driver. Drop the ad-hoc version. Signed-off-by: Bin Meng <bmeng.cn@gmail.com> Reviewed-by: Simon Glass <sjg@chromium.org> Tested-by: Simon Glass <sjg@chromium.org>
* spi: ich: Use compatible strings to distinguish controller versionBin Meng2016-02-05-7/+7
| | | | | | | | | | At present ich spi driver gets the controller version information via pch, but this can be simply retrieved via spi node's compatible string. Signed-off-by: Bin Meng <bmeng.cn@gmail.com> Reviewed-by: Simon Glass <sjg@chromium.org> Reviewed-by: Jagan Teki <jteki@openedev.com> Tested-by: Simon Glass <sjg@chromium.org>
* x86: Correct spi node aliasBin Meng2016-01-28-14/+14
| | | | | | | | With recent changes spi node was moved to a place as a subnode under pch, so update the alias to refer to its correct place as well. Signed-off-by: Bin Meng <bmeng.cn@gmail.com> Reviewed-by: Simon Glass <sjg@chromium.org>
* x86: config option for loading ACPI table from QEMUMiao Yan2016-01-28-0/+9
| | | | | | | | | This patch adds a config option for loading ACPI table from QEMU. When enabled, U-Boot won't generate ACPI tables, but use those provided by QEMU. Signed-off-by: Miao Yan <yanmiaobest@gmail.com> Reviewed-by: Bin Meng <bmeng.cn@gmail.com> Tested-by: Bin Meng <bmeng.cn@gmail.com>
* x86: qemu: add the ability to load and link ACPI tables from QEMUMiao Yan2016-01-28-0/+322
| | | | | | | | | | | This patch adds the ability to load and link ACPI tables provided by QEMU. QEMU tells guests how to load and patch ACPI tables through its fw_cfg interface, by adding a firmware file 'etc/table-loader'. Guests are supposed to parse this file and execute corresponding QEMU commands. Signed-off-by: Miao Yan <yanmiaobest@gmail.com> Reviewed-by: Bin Meng <bmeng.cn@gmail.com> Tested-by: Bin Meng <bmeng.cn@gmail.com>
* x86: qemu: setup PM IO base for ACPI in southbridgeMiao Yan2016-01-28-0/+43
| | | | | | | | Enable ACPI IO space for piix4 (for pc board) and ich9 (for q35 board) Signed-off-by: Miao Yan <yanmiaobest@gmail.com> Reviewed-by: Bin Meng <bmeng.cn@gmail.com> Tested-by: Bin Meng <bmeng.cn@gmail.com>
* x86: qemu: re-structure qemu_fwcfg_list_firmware()Miao Yan2016-01-28-17/+55
| | | | | | | | | Re-write the logic in qemu_fwcfg_list_firmware(), add a function qemu_fwcfg_read_firmware_list() to handle reading firmware list. Signed-off-by: Miao Yan <yanmiaobest@gmail.com> Reviewed-by: Bin Meng <bmeng.cn@gmail.com> Tested-by: Bin Meng <bmeng.cn@gmail.com>
* x86: baytrail: Add option to disable the internal UART to setup_early_uart()Stefan Roese2016-01-28-5/+9
| | | | | | | | | | | This patch adds a parameter to the function setup_early_uart() to either enable or disable the internal BayTrail legacy UART. Since the name setup_early_uart() does not match its functionality any more, lets rename it to setup_internal_uart() as well in this patch. Signed-off-by: Stefan Roese <sr@denx.de> Reviewed-by: Bin Meng <bmeng.cn@gmail.com> Reviewed-by: Simon Glass <sjg@chromium.org>
* x86: ivybridge: Use syscon for the GMA deviceSimon Glass2016-01-24-15/+17
| | | | | | | | | Until we have a proper video uclass we can use syscon to handle the GMA device, and avoid the special device tree and PCI searching. Update the code to work this way. Signed-off-by: Simon Glass <sjg@chromium.org> Reviewed-by: Bin Meng <bmeng.cn@gmail.com>
* x86: Set up a shared syscon numbering schemaSimon Glass2016-01-24-4/+14
| | | | | | | | | Each system controller can have a number to identify it. It can then be accessed using syscon_get_by_driver_data(). Put this in a shared header file and update the only current user. Signed-off-by: Simon Glass <sjg@chromium.org> Reviewed-by: Bin Meng <bmeng.cn@gmail.com>
* x86: ivybridge: Drop the SMM-locking codeSimon Glass2016-01-24-57/+0
| | | | | | | | U-Boot does not support SMM yet, so we can drop this code. It is easy to bring back when needed. Signed-off-by: Simon Glass <sjg@chromium.org> Reviewed-by: Bin Meng <bmeng.cn@gmail.com>
* x86: ivybridge: Drop XHCI supportSimon Glass2016-01-24-34/+0
| | | | | | | This is not used on link which is the only ivybridge board. Drop this code. Signed-off-by: Simon Glass <sjg@chromium.org> Reviewed-by: Bin Meng <bmeng.cn@gmail.com>
* x86: ivybridge: Drop special EHCI initSimon Glass2016-01-24-34/+12
| | | | | | | | | | This is not needed. On reset wake-on-disconnect is already set. It may a problem during a soft reset or resume, but for now it does not seem important. Also drop the command register update since PCI auto-config does it for us. Signed-off-by: Simon Glass <sjg@chromium.org> Reviewed-by: Bin Meng <bmeng.cn@gmail.com>
* x86: ivybridge: Sort out the calls to bridge_silicon_revision()Simon Glass2016-01-24-42/+46
| | | | | | | | This function is called all over the place. Convert it use the driver model PCI API, and rationalise the calls. Signed-off-by: Simon Glass <sjg@chromium.org> Reviewed-by: Bin Meng <bmeng.cn@gmail.com>
* x86: ivybridge: Move code from pch.c to bd82x6x.cSimon Glass2016-01-24-145/+129
| | | | | | | This code relates to the PCH, so we should move it into the same file. Signed-off-by: Simon Glass <sjg@chromium.org> Reviewed-by: Bin Meng <bmeng.cn@gmail.com>
* x86: ivybridge: Convert pch.c to use DM PCI APISimon Glass2016-01-24-32/+76
| | | | | | | Convert this file to use the driver model PCI API. Signed-off-by: Simon Glass <sjg@chromium.org> Reviewed-by: Bin Meng <bmeng.cn@gmail.com>
* x86: ivybridge: Convert report_platform to DM PCI APISimon Glass2016-01-24-7/+8
| | | | | | | Convert these functions to use the driver model PCI API. Signed-off-by: Simon Glass <sjg@chromium.org> Reviewed-by: Bin Meng <bmeng.cn@gmail.com>
* x86: ivybridge: Convert SDRAM init to use driver modelSimon Glass2016-01-24-38/+101
| | | | | | | | | SDRAM init needs access to the Northbridge controller and the Intel Management Engine device. Add the latter to the device tree and convert all of this code to driver model. Signed-off-by: Simon Glass <sjg@chromium.org> Reviewed-by: Bin Meng <bmeng.cn@gmail.com>
* x86: ivybridge: Convert sdram_initialise() to use DM PCI APISimon Glass2016-01-24-9/+10
| | | | | | | | Convert this function to use the the driver model PCI API. We just need to pass in the northbridge device. Signed-off-by: Simon Glass <sjg@chromium.org> Reviewed-by: Bin Meng <bmeng.cn@gmail.com>
* x86: ivybridge: Convert dram_init() to use DM PCI APISimon Glass2016-01-24-14/+25
| | | | | | | | Convert the top part of the DRAM init to use the driver model PCI API. Further work will complete the transformation. Signed-off-by: Simon Glass <sjg@chromium.org> Reviewed-by: Bin Meng <bmeng.cn@gmail.com>
* x86: ivybridge: Convert enable_usb_bar() to use DM PCI APISimon Glass2016-01-24-17/+17
| | | | | | | | | Convert this function over to use the driver model PCI API. In this case we want to avoid using the real PCI devices since they have not yet been probed. Instead, write directly to their PCI configuration address. Signed-off-by: Simon Glass <sjg@chromium.org> Reviewed-by: Bin Meng <bmeng.cn@gmail.com>
* x86: ivybridge: Use the I2C driver to perform SMbus initSimon Glass2016-01-24-36/+9
| | | | | | | | Move the init code into the I2C driver. Signed-off-by: Simon Glass <sjg@chromium.org> Reviewed-by: Heiko Schocher <hs@denx.de> Reviewed-by: Bin Meng <bmeng.cn@gmail.com>
* x86: ivybridge: Convert lpc init code to DM PCI APISimon Glass2016-01-24-63/+66
| | | | | | | | Adjust this code to use the driver model PCI API. This is all called through lpc_init_extra(). Signed-off-by: Simon Glass <sjg@chromium.org> Reviewed-by: Bin Meng <bmeng.cn@gmail.com>
* x86: ivybridge: Drop the special PCI driverSimon Glass2016-01-24-48/+1
| | | | | | | | There is nothing special about the ivybridge pci driver now, so just use the generic one. Signed-off-by: Simon Glass <sjg@chromium.org> Reviewed-by: Bin Meng <bmeng.cn@gmail.com>
* x86: ivybridge: Move LPC init into the LPC probe() methodSimon Glass2016-01-24-14/+9
| | | | | | | | Drop the lpc_init_extra() function and just use the post-relocation LPC probe() instead. Signed-off-by: Simon Glass <sjg@chromium.org> Reviewed-by: Bin Meng <bmeng.cn@gmail.com>
* x86: ivybridge: Move lpc_enable() into gma.cSimon Glass2016-01-24-9/+4
| | | | | | | | This graphics init code is best placed in the gma init code. Move the code and drop the function. Signed-off-by: Simon Glass <sjg@chromium.org> Reviewed-by: Bin Meng <bmeng.cn@gmail.com>
* x86: ivybridge: Use driver model PCI API in sata.cSimon Glass2016-01-24-49/+45
| | | | | | | Adjust the functions in this file to use the driver model PCI API. Signed-off-by: Simon Glass <sjg@chromium.org> Reviewed-by: Bin Meng <bmeng.cn@gmail.com>
* x86: ivybridge: Use the SATA driver to do the initSimon Glass2016-01-24-10/+8
| | | | | | | | Instead of manually initing the device, probe the SATA device and move the init there. Signed-off-by: Simon Glass <sjg@chromium.org> Reviewed-by: Bin Meng <bmeng.cn@gmail.com>
* x86: ivybridge: Drop the unused bd82x6x_init_extra()Simon Glass2016-01-24-18/+0
| | | | | | | This function does nothing now so can be dropped. Signed-off-by: Simon Glass <sjg@chromium.org> Reviewed-by: Bin Meng <bmeng.cn@gmail.com>
* x86: ivybridge: Do the SATA init before relocationSimon Glass2016-01-24-11/+36
| | | | | | | | | The SATA device needs to set itself up so that it appears correctly on the PCI bus. The easiest way to do this is to set it up to probe before relocation. This can do the early setup. Signed-off-by: Simon Glass <sjg@chromium.org> Reviewed-by: Bin Meng <bmeng.cn@gmail.com>
* x86: ivybridge: Drop unnecessary northbridge setupSimon Glass2016-01-24-20/+0
| | | | | | | This is done by default with PCI auto-config. Drop it. Signed-off-by: Simon Glass <sjg@chromium.org> Reviewed-by: Bin Meng <bmeng.cn@gmail.com>
* x86: ivybridge: Use driver model PCI API in bd82x6x.cSimon Glass2016-01-24-16/+7
| | | | | | | | | Adjust most of the remaining functions in this file to use the driver model PCI API. The one remaining function is bridge_silicon_revision() which will need a little more work. Signed-off-by: Simon Glass <sjg@chromium.org> Reviewed-by: Bin Meng <bmeng.cn@gmail.com>
* x86: ivybridge: Move northbridge and PCH init into driversSimon Glass2016-01-24-47/+12
| | | | | | | | | | Instead of calling the northbridge and PCH init from bd82x6x_init_extra() when the PCI bus is probed, call it from the respective drivers. Also drop the Northbridge init as it has no effect. The registers it touches appear to be read-only. Signed-off-by: Simon Glass <sjg@chromium.org> Reviewed-by: Bin Meng <bmeng.cn@gmail.com>
* x86: Bring up northbridge, pch and lpc after the CPUsSimon Glass2016-01-24-2/+18
| | | | | | | | | | These devices currently need to be inited early in boot. Once we have the init in the right places (with each device doing its own init and no problems with ordering) we should be able to remove this. For now it is needed to keep things working. Signed-off-by: Simon Glass <sjg@chromium.org> Reviewed-by: Bin Meng <bmeng.cn@gmail.com>
* x86: Don't show an error when the MRC cache is up to dateSimon Glass2016-01-24-1/+5
| | | | | | | | | | When the final MRC cache record is the same as the one we want to write, we skip writing since there is no point. This is normal behaviour. Avoiding printing an error when this happens. Signed-off-by: Simon Glass <sjg@chromium.org> Reviewed-by: Bin Meng <bmeng.cn@gmail.com>
* x86: Make x86_init_cpus() staticSimon Glass2016-01-24-3/+1
| | | | | | | | There are no other implementations of this function, and boards that need it can implement a CPU driver. Signed-off-by: Simon Glass <sjg@chromium.org> Reviewed-by: Bin Meng <bmeng.cn@gmail.com>
* x86: ivybridge: Move early init code into northbridge.cSimon Glass2016-01-24-82/+67
| | | | | | | | This code is now part of the northbridge driver, so move it into the same place. Signed-off-by: Simon Glass <sjg@chromium.org> Reviewed-by: Bin Meng <bmeng.cn@gmail.com>
* x86: ivybridge: Drop the dead MTRR codeSimon Glass2016-01-24-10/+0
| | | | | | | This is not used and MTRRs are set up elsewhere now. Drop it. Signed-off-by: Simon Glass <sjg@chromium.org> Reviewed-by: Bin Meng <bmeng.cn@gmail.com>
* x86: ivybridge: Set up the thermal target correctlySimon Glass2016-01-24-11/+10
| | | | | | | | | This uses a non-existent node at present. It should use the first CPU node. The referenced property does not exist (the correct value is the default of 0), but this allows the follow-on init to complete. Signed-off-by: Simon Glass <sjg@chromium.org> Reviewed-by: Bin Meng <bmeng.cn@gmail.com>
* x86: ivybridge: Move CPU init code into the driverSimon Glass2016-01-24-22/+4
| | | | | | | | Use the CPU driver's probe() method to perform the CPU init. This will happen automatically when the first CPU is probed. Signed-off-by: Simon Glass <sjg@chromium.org> Reviewed-by: Bin Meng <bmeng.cn@gmail.com>
* x86: ivybridge: Use common CPU init codeSimon Glass2016-01-24-52/+76
| | | | | | | | | The existing ivybridge code predates the normal multi-core CPU init, and it is not used. Remove it and add CPU nodes to the device tree so that all four CPUs are set up. Also enable the 'cpu' command. Signed-off-by: Simon Glass <sjg@chromium.org> Reviewed-by: Bin Meng <bmeng.cn@gmail.com>
* x86: ivybridge: Move GPIO init to the LPC init() methodSimon Glass2016-01-24-4/+3
| | | | | | | This init can happen in the driver also. Move it. Signed-off-by: Simon Glass <sjg@chromium.org> Reviewed-by: Bin Meng <bmeng.cn@gmail.com>
* x86: ivybridge: Move sandybridge init to the lpc probe() methodSimon Glass2016-01-24-17/+18
| | | | | | | | The watchdog can be reset later when probing the LPC after relocation. Move it. Signed-off-by: Simon Glass <sjg@chromium.org> Reviewed-by: Bin Meng <bmeng.cn@gmail.com>
* x86: ivybridge: Move graphics init much laterSimon Glass2016-01-24-78/+76
| | | | | | | | We don't need to init the graphics controller so early. Move it alongside the other graphics setup, just before we run the ROM. Signed-off-by: Simon Glass <sjg@chromium.org> Reviewed-by: Bin Meng <bmeng.cn@gmail.com>
* x86: ivybridge: Probe the LPC in CPU initSimon Glass2016-01-24-3/+2
| | | | | | | | We can drop the explicit probe of the PCH since the LPC is a child device and this will happen automatically. Signed-off-by: Simon Glass <sjg@chromium.org> Reviewed-by: Bin Meng <bmeng.cn@gmail.com>
generated by cgit v1.1 at 2024-10-22 12:30:03 +0000