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| author | Simon Glass <sjg@chromium.org> | 2016-01-17 16:11:57 -0700 |
|---|---|---|
| committer | Bin Meng <bmeng.cn@gmail.com> | 2016-01-24 12:09:42 +0800 |
| commit | 67292e4c27de6cde4624ce03b47b2449a9ebc671 (patch) | |
| tree | eadaf471a4628230aaf6857d6e4703a630c8ef7d /arch/x86 | |
| parent | b2a6235920e2c0cd77b6826e9508401426f4ad92 (diff) | |
| download | u-boot-imx-67292e4c27de6cde4624ce03b47b2449a9ebc671.zip u-boot-imx-67292e4c27de6cde4624ce03b47b2449a9ebc671.tar.gz u-boot-imx-67292e4c27de6cde4624ce03b47b2449a9ebc671.tar.bz2 | |
x86: ivybridge: Drop the SMM-locking code
U-Boot does not support SMM yet, so we can drop this code. It is easy to
bring back when needed.
Signed-off-by: Simon Glass <sjg@chromium.org>
Reviewed-by: Bin Meng <bmeng.cn@gmail.com>
Diffstat (limited to 'arch/x86')
| -rw-r--r-- | arch/x86/cpu/ivybridge/lpc.c | 57 |
1 files changed, 0 insertions, 57 deletions
diff --git a/arch/x86/cpu/ivybridge/lpc.c b/arch/x86/cpu/ivybridge/lpc.c index 12e86cb..9ab5ed3 100644 --- a/arch/x86/cpu/ivybridge/lpc.c +++ b/arch/x86/cpu/ivybridge/lpc.c @@ -379,59 +379,6 @@ static void enable_clock_gating(struct udevice *pch) setbits_le32(RCB_REG(0x3564), 0x3); } -#if CONFIG_HAVE_SMI_HANDLER -static void pch_lock_smm(pci_dev_t dev) -{ -#if TEST_SMM_FLASH_LOCKDOWN - u8 reg8; -#endif - - if (acpi_slp_type != 3) { -#if ENABLE_ACPI_MODE_IN_COREBOOT - debug("Enabling ACPI via APMC:\n"); - outb(0xe1, 0xb2); /* Enable ACPI mode */ - debug("done.\n"); -#else - debug("Disabling ACPI via APMC:\n"); - outb(0x1e, 0xb2); /* Disable ACPI mode */ - debug("done.\n"); -#endif - } - - /* Don't allow evil boot loaders, kernels, or - * userspace applications to deceive us: - */ - smm_lock(); - -#if TEST_SMM_FLASH_LOCKDOWN - /* Now try this: */ - debug("Locking BIOS to RO... "); - reg8 = x86_pci_read_config8(dev, 0xdc); /* BIOS_CNTL */ - debug(" BLE: %s; BWE: %s\n", (reg8 & 2) ? "on" : "off", - (reg8 & 1) ? "rw" : "ro"); - reg8 &= ~(1 << 0); /* clear BIOSWE */ - x86_pci_write_config8(dev, 0xdc, reg8); - reg8 |= (1 << 1); /* set BLE */ - x86_pci_write_config8(dev, 0xdc, reg8); - debug("ok.\n"); - reg8 = x86_pci_read_config8(dev, 0xdc); /* BIOS_CNTL */ - debug(" BLE: %s; BWE: %s\n", (reg8 & 2) ? "on" : "off", - (reg8 & 1) ? "rw" : "ro"); - - debug("Writing:\n"); - writeb(0, 0xfff00000); - debug("Testing:\n"); - reg8 |= (1 << 0); /* set BIOSWE */ - x86_pci_write_config8(dev, 0xdc, reg8); - - reg8 = x86_pci_read_config8(dev, 0xdc); /* BIOS_CNTL */ - debug(" BLE: %s; BWE: %s\n", (reg8 & 2) ? "on" : "off", - (reg8 & 1) ? "rw" : "ro"); - debug("Done.\n"); -#endif -} -#endif - static void pch_disable_smm_only_flashing(struct udevice *pch) { u8 reg8; @@ -596,10 +543,6 @@ static int lpc_init_extra(struct udevice *dev) pch_disable_smm_only_flashing(pch); -#if CONFIG_HAVE_SMI_HANDLER - pch_lock_smm(dev); -#endif - pch_fixups(pch); return 0; |