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* x86: baytrail: Add GPIO ASL descriptionBin Meng2016-05-23-0/+98
* x86: baytrail: Add internal UART ASL descriptionBin Meng2016-05-23-0/+64
* x86: acpi: Switch to ACPI mode by ourselves instead of requested by OSPMBin Meng2016-05-23-0/+3
* x86: Prepare configuration tables in dedicated high memory regionBin Meng2016-05-23-0/+23
* x86: qemu: Move qfw command over to cmd and add Kconfig entryTom Rini2016-05-23-157/+0
* x86: baytrail: Add platform ASL filesBin Meng2016-05-23-0/+1348
* x86: acpi: Return table length in acpi_create_madt_lapics()Bin Meng2016-05-23-1/+1
* x86: acpi: Add some generic ASL librariesBin Meng2016-05-23-0/+331
* x86: acpi: Clean up table header revisionsBin Meng2016-05-23-6/+0
* x86: acpi: Use u32 in table write routinesBin Meng2016-05-23-2/+2
* x86: acpi: Adjust order in acpi_table.cBin Meng2016-05-23-7/+7
* x86: acpi: Change fill_header()Bin Meng2016-05-23-0/+1
* x86: acpi: Remove acpi_create_ssdt_generator()Bin Meng2016-05-23-3/+0
* x86: acpi: Reorder code in acpi_table.hBin Meng2016-05-23-178/+169
* x86: acpi: Various changes to acpi_table.hBin Meng2016-05-23-34/+38
* x86: acpi: Remove unused codesBin Meng2016-05-23-68/+0
* x86: irq: Enable SCI on IRQ9Bin Meng2016-05-23-0/+4
* x86: Drop asm/acpi.hBin Meng2016-05-23-24/+0
* x86: Add common SDRAM-init codeSimon Glass2016-03-17-0/+55
* x86: Move common PCH code into a common placeSimon Glass2016-03-17-53/+56
* x86: Add a function to set the IOAPIC IDSimon Glass2016-03-17-0/+2
* x86: broadwell: Add support for SDRAM setupSimon Glass2016-03-17-0/+201
* x86: broadwell: Add power-control supportSimon Glass2016-03-17-0/+129
* x86: broadwell: Add an LPC driverSimon Glass2016-03-17-0/+32
* x86: broadwell: Add a pinctrl driverSimon Glass2016-03-17-0/+91
* x86: broadwell: Add a PCH driverSimon Glass2016-03-17-0/+153
* x86: Add basic support for broadwellSimon Glass2016-03-17-0/+446
* x86: Add support for running Intel reference codeSimon Glass2016-03-17-0/+12
* x86: Drop all the old pin configuration codeSimon Glass2016-03-17-141/+0
* x86: Add an ICH6 pin configuration driverSimon Glass2016-03-17-0/+1
* x86: Update microcode for secondary CPUsSimon Glass2016-03-17-0/+3
* x86: Record the CPU details when starting each coreSimon Glass2016-03-17-0/+9
* x86: Allow I/O functions to use pointersSimon Glass2016-03-17-2/+10
* x86: Add macros to clear and set I/O bitsSimon Glass2016-03-17-0/+22
* x86: ivybridge: Drop sandybridge_early_init()Simon Glass2016-03-17-2/+0
* x86: Move Intel Management Engine code to a common placeSimon Glass2016-03-17-334/+393
* x86: Rename PORT_RESET to IO_PORT_RESETSimon Glass2016-03-17-1/+1
* x86: Move common CPU code to its own placeSimon Glass2016-03-17-2/+44
* x86: Move common LPC code to its own placeSimon Glass2016-03-17-2/+59
* x86: Add the root-complex block to common intel registersSimon Glass2016-03-17-5/+4
* x86: Create a common header for Intel register accessSimon Glass2016-03-17-3/+15
* x86: Move microcode code to a common locationSimon Glass2016-03-17-0/+0
* x86: cpu: Add functions to return the family and steppingSimon Glass2016-03-17-0/+14
* x86: Add comments to the SIPI vectorSimon Glass2016-03-17-0/+1
* x86: Correct duplicate POST valuesSimon Glass2016-03-17-2/+2
* x86: gpio: Correct GPIO setup orderingSimon Glass2016-03-17-0/+5
* x86: Add some more common MSR indexesSimon Glass2016-03-17-18/+40
* x86: Support booting SeaBIOSBin Meng2016-03-17-0/+3
* x86: Implement functions for writing coreboot tableBin Meng2016-03-17-0/+10
* x86: Change write_acpi_tables() signature a little bitBin Meng2016-03-17-1/+1
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