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* x86: dts: link: Add board ID GPIOsSimon Glass2016-03-17-0/+2
* x86: dts: link: Move SPD info into the memory controllerSimon Glass2016-03-17-111/+110
* x86: link: Add required GPIO propertiesSimon Glass2016-03-17-3/+9
* x86: Add Intel Cougar Canyon 2 boardBin Meng2016-02-21-0/+105
* x86: minnowmax: Drop io-base property in the pch_pinctrl nodeBin Meng2016-02-05-1/+0
* x86: ich6_gpio: Convert to use proper DM APIBin Meng2016-02-05-153/+163
* spi: ich: Use compatible strings to distinguish controller versionBin Meng2016-02-05-7/+7
* x86: Correct spi node aliasBin Meng2016-01-28-14/+14
* x86: ivybridge: Use syscon for the GMA deviceSimon Glass2016-01-24-1/+2
* x86: ivybridge: Drop special EHCI initSimon Glass2016-01-24-0/+12
* x86: ivybridge: Convert SDRAM init to use driver modelSimon Glass2016-01-24-0/+6
* x86: ivybridge: Use the I2C driver to perform SMbus initSimon Glass2016-01-24-0/+6
* x86: ivybridge: Drop the special PCI driverSimon Glass2016-01-24-1/+1
* x86: ivybridge: Do the SATA init before relocationSimon Glass2016-01-24-7/+9
* x86: ivybridge: Use common CPU init codeSimon Glass2016-01-24-0/+34
* x86: ivybridge: Add a driver for the bd82x6x northbridgeSimon Glass2016-01-24-0/+7
* x86: ivybridge: Move lpc_early_init() to probe()Simon Glass2016-01-24-2/+1
* x86: ivybridge: Set up the LPC device using driver modelSimon Glass2016-01-24-0/+1
* dm: x86: queensbay: Add an interrupt driverSimon Glass2016-01-24-1/+1
* dm: x86: quark: Add an interrupt driverSimon Glass2016-01-24-1/+1
* dm: x86: spi: Convert ICH SPI driver to driver model PCI APISimon Glass2016-01-24-323/+371
* x86: qemu: remove cpu node in device treeMiao Yan2016-01-13-14/+0
* x86: qemu: add a cpu uclass driver for qemu targetMiao Yan2016-01-13-4/+4
* x86: ivybridge: Add microcode blobs for all the steppingsBin Meng2016-01-13-0/+2472
* x86: Fix PCI UART compatible string for crownbay and galileoBin Meng2015-12-09-5/+5
* x86: Convert to use driver model timerBin Meng2015-12-01-0/+32
* ns16550: unify serial_x86Thomas Chou2015-11-20-1/+1
* x86: qemu: Convert to use driver model keyboardBin Meng2015-11-19-0/+2
* x86: crownbay: Convert to use driver model keyboardBin Meng2015-11-19-0/+1
* x86: Add an i8042 device for boards that have itSimon Glass2015-11-19-0/+11
* Various Makefiles: Add SPDX-License-Identifier tagsTom Rini2015-11-10-0/+4
* x86: Add support for Advantech SOM-6896George McCollister2015-10-21-1/+45
* x86: galileo: Enable mrc cacheBin Meng2015-10-21-0/+4
* x86: Remove unused rw-mrc-cache properties in the link and panther dts filesBin Meng2015-10-21-5/+0
* x86: Enable mrc cache for bayleybay and minnowmaxBin Meng2015-10-21-0/+12
* x86: galileo: Add PCIe root port IRQ routingBin Meng2015-09-16-0/+12
* x86: Convert to use driver model pci on quark/galileoBin Meng2015-09-09-2/+6
* x86: panther: Add PCI and video configurationSimon Glass2015-09-09-0/+10
* exynos: x86: dts: Add tpm nodes to the device tree for Chrome OS devicesSimon Glass2015-08-31-0/+10
* x86: crownbay: Support Topcliff integrated pci uart devices with driver modelBin Meng2015-08-26-5/+10
* x86: crownbay: Enable on-board SMSC superio keyboard controllerBin Meng2015-08-26-1/+1
* x86: minnowmax: Correct pad-offset value for host_en1Simon Glass2015-08-26-1/+1
* x86: minnowmax: Add access to GPIOs E0, E1, E2Simon Glass2015-08-26-0/+27
* x86: baytrail: Support multiple microcode copiesBin Meng2015-08-26-0/+9
* x86: baytrail: Add microcode for BayTrail-I D0 steppingBin Meng2015-08-26-0/+3284
* x86: minnowmax: Define and enable interrupt setupSimon Glass2015-08-14-3/+66
* x86: baytrail: Configure FSP UPD from device treeAndrew Bradford2015-08-14-0/+94
* x86: dts: Add a device tree file for EFISimon Glass2015-08-05-0/+23
* x86: bayleybay: Configure PCI IRQBin Meng2015-08-05-0/+63
* x86: Add Intel Bayley Bay board supportBin Meng2015-08-05-1/+136
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