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| author | Simon Glass <sjg@chromium.org> | 2016-01-17 16:11:23 -0700 |
|---|---|---|
| committer | Bin Meng <bmeng.cn@gmail.com> | 2016-01-24 12:08:17 +0800 |
| commit | bba22a97a7e143560b137c9a2d9fcf6dbd038470 (patch) | |
| tree | ff9fab403ba77b9ef830a31ebc0979802b03f864 /arch/x86/dts | |
| parent | 9fd11c7a8ce8745fcfee4b86e6b9217f738d3ff4 (diff) | |
| download | u-boot-imx-bba22a97a7e143560b137c9a2d9fcf6dbd038470.zip u-boot-imx-bba22a97a7e143560b137c9a2d9fcf6dbd038470.tar.gz u-boot-imx-bba22a97a7e143560b137c9a2d9fcf6dbd038470.tar.bz2 | |
x86: ivybridge: Use common CPU init code
The existing ivybridge code predates the normal multi-core CPU init, and
it is not used. Remove it and add CPU nodes to the device tree so that all
four CPUs are set up. Also enable the 'cpu' command.
Signed-off-by: Simon Glass <sjg@chromium.org>
Reviewed-by: Bin Meng <bmeng.cn@gmail.com>
Diffstat (limited to 'arch/x86/dts')
| -rw-r--r-- | arch/x86/dts/chromebook_link.dts | 34 |
1 files changed, 34 insertions, 0 deletions
diff --git a/arch/x86/dts/chromebook_link.dts b/arch/x86/dts/chromebook_link.dts index e2c722d..3ed6662 100644 --- a/arch/x86/dts/chromebook_link.dts +++ b/arch/x86/dts/chromebook_link.dts @@ -18,6 +18,40 @@ silent_console = <0>; }; + cpus { + #address-cells = <1>; + #size-cells = <0>; + + cpu@0 { + device_type = "cpu"; + compatible = "intel,core-gen3"; + reg = <0>; + intel,apic-id = <0>; + }; + + cpu@1 { + device_type = "cpu"; + compatible = "intel,core-gen3"; + reg = <1>; + intel,apic-id = <1>; + }; + + cpu@2 { + device_type = "cpu"; + compatible = "intel,core-gen3"; + reg = <2>; + intel,apic-id = <2>; + }; + + cpu@3 { + device_type = "cpu"; + compatible = "intel,core-gen3"; + reg = <3>; + intel,apic-id = <3>; + }; + + }; + gpioa { compatible = "intel,ich6-gpio"; u-boot,dm-pre-reloc; |