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* x86: Setup fixed range MTRRs for legacy regionsBin Meng2015-07-14-0/+22
* x86: queensbay: Change PCIe root ports' interrupt routingBin Meng2015-07-14-6/+7
* x86: Remove inline for lapic access routinesBin Meng2015-07-14-27/+143
* x86: Add I/O APIC register access routinesBin Meng2015-07-14-1/+22
* x86: Reduce PIRQ routing table sizeBin Meng2015-07-14-9/+56
* x86: Ignore function number when writing PIRQ routing tableBin Meng2015-07-14-4/+3
* x86: Write correct bus number for the irq routerBin Meng2015-07-14-1/+1
* x86: Clean up lapic codesBin Meng2015-07-14-22/+18
* x86: Move lapic_setup() call into init_bsp()Bin Meng2015-07-14-3/+1
* x86: Move MP initialization codes into a common placeBin Meng2015-07-14-72/+112
* x86: ivybridge: Remove SMP from CPU_SPECIFIC_OPTIONSBin Meng2015-07-14-1/+0
* x86: dm: Clean up cpu driversBin Meng2015-07-14-41/+52
* x86: fsp: Move FspInitEntry call to board_init_f()Bin Meng2015-07-14-1/+5
* x86: fsp: Load GDT before calling FspInitEntryBin Meng2015-07-14-2/+23
* x86: Add Kconfig options to be used by arch/x86/cpu/config.mkBin Meng2015-07-14-3/+3
* x86: baytrail: pci region 3 is not always mapped to end of ramAndrew Bradford2015-06-04-1/+1
* x86: qemu: Implement PIRQ routingBin Meng2015-06-04-0/+13
* x86: coreboot: Control I/O port 0xb2 writing via device treeBin Meng2015-06-04-3/+9
* x86: coreboot: Fix cosmetic issuesBin Meng2015-06-04-24/+3
* x86: qemu: Adjust VGA initializationBin Meng2015-06-04-19/+15
* x86: qemu: Enable legacy IDE I/O ports decodeBin Meng2015-06-04-0/+14
* x86: qemu: Turn on legacy segments decodeBin Meng2015-06-04-0/+20
* x86: Do sanity test on pirq table before writingBin Meng2015-06-04-0/+3
* x86: quark: Implement PIRQ routingBin Meng2015-06-04-0/+31
* x86: Refactor PIRQ routing supportBin Meng2015-06-04-245/+253
* x86: qemu: Add graphics supportBin Meng2015-06-04-1/+23
* x86: Support QEMU x86 targetsBin Meng2015-06-04-0/+188
* x86: Add a CPU driver for baytrailSimon Glass2015-04-30-0/+206
* x86: Allow CPUs to be set up after relocationSimon Glass2015-04-30-0/+38
* x86: Add multi-processor initSimon Glass2015-04-30-2/+717
* x86: Provide access to the IDTSimon Glass2015-04-29-0/+5
* x86: Store the GDT pointer in global_dataSimon Glass2015-04-29-0/+1
* x86: Disable -WerrorSimon Glass2015-04-29-1/+1
* x86: Remove unwanted MMC debuggingSimon Glass2015-04-29-1/+0
* x86: quark: Use reset_cpu()Simon Glass2015-04-29-1/+1
* x86: ivybridge: Use reset_cpu()Simon Glass2015-04-29-15/+6
* x86: Implement reset_cpu() correctly for modern CPUsSimon Glass2015-04-29-13/+9
* x86: link: Add PCH driver to support SPI FlashSimon Glass2015-04-29-0/+11
* x86: quark: Turn on legacy segments decodeBin Meng2015-04-29-0/+12
* x86: queensbay: Implement PIRQ routingBin Meng2015-04-29-2/+252
* x86: Write configuration tables in last_stage_init()Bin Meng2015-04-29-0/+10
* x86: Add a function to assign IRQ numbers to PCI deviceBin Meng2015-04-29-0/+21
* x86: queensbay: Avoid using PCH prefixBin Meng2015-04-29-2/+2
* Kconfig: Move CONFIG_BOOTSTAGE to KconfigSimon Glass2015-04-18-1/+1
* x86: chromebook_link: dts: Add PCH and LPC devicesSimon Glass2015-04-18-2/+13
* dm: x86: Add a uclass for a Platform Controller HubSimon Glass2015-04-18-9/+0
* dm: x86: spi: Convert ICH SPI driver to driver modelSimon Glass2015-04-18-10/+14
* dm: x86: pci: Convert chromebook_link to use driver model for pciSimon Glass2015-04-18-65/+57
* dm: x86: pci: Convert coreboot to use driver model for pciSimon Glass2015-04-18-47/+16
* dm: x86: pci: Add a PCI driver for driver modelSimon Glass2015-04-18-0/+40
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