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authorBin Meng <bmeng.cn@gmail.com>2015-07-06 16:31:30 +0800
committerSimon Glass <sjg@chromium.org>2015-07-14 18:03:18 -0600
commit43dd22f5fc4c368616721a69e5ea0769abf292dc (patch)
treeabe7a052d68f5ac9687cef6afdf3a9913e11e09b /arch/x86/cpu
parent0e98a1473a85f2d8590f97653a36f90f55267732 (diff)
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x86: Setup fixed range MTRRs for legacy regions
We should setup fixed range MTRRs for some legacy regions like VGA RAM and PCI ROM areas as uncacheable. Note FSP may setup these to other cache settings, but we can override this in x86_cpu_init_f(). Signed-off-by: Bin Meng <bmeng.cn@gmail.com> Acked-by: Simon Glass <sjg@chromium.org>
Diffstat (limited to 'arch/x86/cpu')
-rw-r--r--arch/x86/cpu/cpu.c22
1 files changed, 22 insertions, 0 deletions
diff --git a/arch/x86/cpu/cpu.c b/arch/x86/cpu/cpu.c
index d108ee5..9afdafb 100644
--- a/arch/x86/cpu/cpu.c
+++ b/arch/x86/cpu/cpu.c
@@ -28,6 +28,8 @@
#include <asm/cpu.h>
#include <asm/lapic.h>
#include <asm/mp.h>
+#include <asm/msr.h>
+#include <asm/mtrr.h>
#include <asm/post.h>
#include <asm/processor.h>
#include <asm/processor-flags.h>
@@ -352,6 +354,26 @@ int x86_cpu_init_f(void)
gd->arch.has_mtrr = has_mtrr();
}
+ /* Configure fixed range MTRRs for some legacy regions */
+ if (gd->arch.has_mtrr) {
+ u64 mtrr_cap;
+
+ mtrr_cap = native_read_msr(MTRR_CAP_MSR);
+ if (mtrr_cap & MTRR_CAP_FIX) {
+ /* Mark the VGA RAM area as uncacheable */
+ native_write_msr(MTRR_FIX_16K_A0000_MSR, 0, 0);
+
+ /* Mark the PCI ROM area as uncacheable */
+ native_write_msr(MTRR_FIX_4K_C0000_MSR, 0, 0);
+ native_write_msr(MTRR_FIX_4K_C8000_MSR, 0, 0);
+ native_write_msr(MTRR_FIX_4K_D0000_MSR, 0, 0);
+ native_write_msr(MTRR_FIX_4K_D8000_MSR, 0, 0);
+
+ /* Enable the fixed range MTRRs */
+ msr_setbits_64(MTRR_DEF_TYPE_MSR, MTRR_DEF_TYPE_FIX_EN);
+ }
+ }
+
return 0;
}