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| author | Simon Glass <sjg@chromium.org> | 2015-03-26 09:29:26 -0600 |
|---|---|---|
| committer | Simon Glass <sjg@chromium.org> | 2015-04-18 11:11:14 -0600 |
| commit | ba4575626eddef71b5a8dc26dc4b267918b9438c (patch) | |
| tree | 60e47b89a76b5d69b41669a4afeb653ec02f8525 /arch/x86/cpu | |
| parent | 8d987abc6a8553454b0b602b46a5dc09a4687110 (diff) | |
| download | u-boot-imx-ba4575626eddef71b5a8dc26dc4b267918b9438c.zip u-boot-imx-ba4575626eddef71b5a8dc26dc4b267918b9438c.tar.gz u-boot-imx-ba4575626eddef71b5a8dc26dc4b267918b9438c.tar.bz2 | |
dm: x86: spi: Convert ICH SPI driver to driver model
Convert this driver over to use driver model. Since all x86 platforms use
it, move x86 to use driver model for SPI and SPI flash. Adjust all dependent
code and remove the old x86 spi_init() function.
Note that this does not make full use of the new PCI uclass as yet. We still
scan the bus looking for the device. It should move to finding its details
in the device tree.
Signed-off-by: Simon Glass <sjg@chromium.org>
Diffstat (limited to 'arch/x86/cpu')
| -rw-r--r-- | arch/x86/cpu/ivybridge/mrccache.c | 7 | ||||
| -rw-r--r-- | arch/x86/cpu/ivybridge/sdram.c | 17 |
2 files changed, 14 insertions, 10 deletions
diff --git a/arch/x86/cpu/ivybridge/mrccache.c b/arch/x86/cpu/ivybridge/mrccache.c index 0f1a64b..9205494 100644 --- a/arch/x86/cpu/ivybridge/mrccache.c +++ b/arch/x86/cpu/ivybridge/mrccache.c @@ -105,7 +105,7 @@ static struct mrc_data_container *find_next_mrc_cache(struct fmap_entry *entry, return cache; } -int mrccache_update(struct spi_flash *sf, struct fmap_entry *entry, +int mrccache_update(struct udevice *sf, struct fmap_entry *entry, struct mrc_data_container *cur) { struct mrc_data_container *cache; @@ -135,7 +135,7 @@ int mrccache_update(struct spi_flash *sf, struct fmap_entry *entry, debug("Erasing the MRC cache region of %x bytes at %x\n", entry->length, entry->offset); - ret = spi_flash_erase(sf, entry->offset, entry->length); + ret = spi_flash_erase_dm(sf, entry->offset, entry->length); if (ret) { debug("Failed to erase flash region\n"); return ret; @@ -146,7 +146,8 @@ int mrccache_update(struct spi_flash *sf, struct fmap_entry *entry, /* Write the data out */ offset = (ulong)cache - base_addr + entry->offset; debug("Write MRC cache update to flash at %lx\n", offset); - ret = spi_flash_write(sf, offset, cur->data_size + sizeof(*cur), cur); + ret = spi_flash_write_dm(sf, offset, cur->data_size + sizeof(*cur), + cur); if (ret) { debug("Failed to write to SPI flash\n"); return ret; diff --git a/arch/x86/cpu/ivybridge/sdram.c b/arch/x86/cpu/ivybridge/sdram.c index 672d069..9a6da37 100644 --- a/arch/x86/cpu/ivybridge/sdram.c +++ b/arch/x86/cpu/ivybridge/sdram.c @@ -89,11 +89,12 @@ void dram_init_banksize(void) } } -static int get_mrc_entry(struct spi_flash **sfp, struct fmap_entry *entry) +static int get_mrc_entry(struct udevice **devp, struct fmap_entry *entry) { const void *blob = gd->fdt_blob; int node, spi_node, mrc_node; int upto; + int ret; /* Find the flash chip within the SPI controller node */ upto = 0; @@ -112,10 +113,13 @@ static int get_mrc_entry(struct spi_flash **sfp, struct fmap_entry *entry) if (fdtdec_read_fmap_entry(blob, mrc_node, "rm-mrc-cache", entry)) return -EINVAL; - if (sfp) { - *sfp = spi_flash_probe_fdt(blob, node, spi_node); - if (!*sfp) - return -EBADF; + if (devp) { + debug("getting sf\n"); + ret = uclass_get_device_by_of_offset(UCLASS_SPI_FLASH, node, + devp); + debug("ret = %d\n", ret); + if (ret) + return ret; } return 0; @@ -246,7 +250,7 @@ static int sdram_save_mrc_data(void) { struct mrc_data_container *data; struct fmap_entry entry; - struct spi_flash *sf; + struct udevice *sf; int ret; if (!gd->arch.mrc_output_len) @@ -266,7 +270,6 @@ static int sdram_save_mrc_data(void) free(data); err_data: - spi_flash_free(sf); err_entry: if (ret) debug("%s: Failed: %d\n", __func__, ret); |