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path: root/arch/x86/cpu/ivybridge
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* x86: Convert to use driver model timerBin Meng2015-12-01-1/+0
* x86: ivybridge: Enable the MRC cacheBin Meng2015-10-21-8/+2
* x86: ivybridge: Measure the MRC code execution timeSimon Glass2015-10-21-0/+3
* x86: ivybridge: Fix car_uninit() to correctly set run stateSimon Glass2015-10-21-1/+1
* x86: ivybridge: Check the RTC return valueSimon Glass2015-10-21-3/+10
* x86: ivybridge: Use 'ret' instead of 'rcode'Simon Glass2015-10-21-8/+8
* x86: chromebook_link: Enable the debug UARTSimon Glass2015-10-21-0/+7
* x86: ivybridge: Correct two typos for MRCBin Meng2015-10-21-2/+2
* x86: Use struct mrc_region to describe a mrc regionBin Meng2015-10-21-1/+1
* x86: ivybridge: Use APIs provided in the mrccache libBin Meng2015-10-21-108/+4
* x86: Move mrccache.[c|h] to a common placeBin Meng2015-10-21-159/+1
* x86: ivybridge: Remove the dead codes that programs pci bridgeBin Meng2015-10-21-32/+0
* x86: Enable DM RTC support for all x86 boardsBin Meng2015-07-28-9/+24
* Kill unneeded #include <linux/kconfig.h>Masahiro Yamada2015-07-27-1/+0
* x86: Clean up lapic codesBin Meng2015-07-14-1/+1
* x86: ivybridge: Remove SMP from CPU_SPECIFIC_OPTIONSBin Meng2015-07-14-1/+0
* x86: Add multi-processor initSimon Glass2015-04-30-2/+3
* x86: ivybridge: Use reset_cpu()Simon Glass2015-04-29-15/+6
* x86: chromebook_link: dts: Add PCH and LPC devicesSimon Glass2015-04-18-2/+13
* dm: x86: Add a uclass for a Platform Controller HubSimon Glass2015-04-18-9/+0
* dm: x86: spi: Convert ICH SPI driver to driver modelSimon Glass2015-04-18-10/+14
* dm: x86: pci: Convert chromebook_link to use driver model for pciSimon Glass2015-04-18-65/+57
* x86: Split up arch_cpu_init()Simon Glass2015-04-16-0/+8
* x86: Add a x86_ prefix to the x86-specific PCI functionsSimon Glass2015-04-16-163/+166
* x86: video: Allow video ROM execution to fall back to the other methodSimon Glass2015-02-05-1/+2
* x86: Rename MMCONF_BASE_ADDRESS and make it common across x86Simon Glass2015-02-05-1/+1
* x86: ivybridge: Drop the Kconfig MRC cache informationSimon Glass2015-01-24-28/+0
* x86: Implement a cache for Memory Reference Code parametersSimon Glass2015-01-24-0/+410
* x86: ivybridge: Update microcode early in bootSimon Glass2015-01-13-10/+34
* x86: ivybridge: Add a way to turn off the CARSimon Glass2015-01-13-0/+46
* x86: ivybridge: Request MTRRs for DRAM regionsSimon Glass2015-01-13-0/+10
* x86: ivybridge: Set up an MTRR for the video frame bufferSimon Glass2015-01-13-0/+7
* x86: Add support for MTRRsSimon Glass2015-01-13-6/+6
* x86: ivybridge: Drop support for ROM cachingSimon Glass2015-01-13-25/+0
* x86: ivybridge: Only run the Video BIOS when video is enabledSimon Glass2015-01-13-1/+8
* x86: Use consistent name XXX_ADDR for binary blob flash addressBin Meng2014-12-18-1/+1
* x86: Correct problems in the microcode loadingSimon Glass2014-12-18-10/+15
* x86: ivybridge: Update the microcodeSimon Glass2014-12-18-0/+2
* x86: Add post failure codes for bist and carBin Meng2014-12-13-0/+1
* x86: Add initial video device init for Intel GMASimon Glass2014-11-25-1/+925
* x86: ivybridge: Add northbridge init functionsSimon Glass2014-11-25-0/+191
* x86: Add init for model 206AX CPUSimon Glass2014-11-25-0/+521
* x86: ivybridge: Set up XHCI USBSimon Glass2014-11-25-0/+33
* x86: ivybridge: Set up EHCI USBSimon Glass2014-11-25-0/+32
* x86: ivybridge: Add SATA initSimon Glass2014-11-25-0/+246
* x86: ivybridge: Add additional LPC initSimon Glass2014-11-25-1/+528
* x86: ivybridge: Add PCH initSimon Glass2014-11-25-0/+124
* x86: ivybridge: Add support for BD82x6x PCHSimon Glass2014-11-25-0/+140
* x86: ivybridge: Implement SDRAM initSimon Glass2014-11-21-1/+1031
* x86: ivybridge: Add LAPIC supportSimon Glass2014-11-21-0/+3
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