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* arch/powerpc/cpu/mpc85xx/cpu_init.c: Fix GCC 4.6 build warningKumar Gala2011-11-11-2/+1
| | | | | | | | | Fix: cpu_init.c: In function 'cpu_init_r': cpu_init.c:320:7: warning: variable 'l2srbar' set but not used [-Wunused-but-set-variable] Signed-off-by: Kumar Gala <galak@kernel.crashing.org>
* powerpc/mpc8548: Add workaround for erratum NMG_LBC103Kumar Gala2011-10-03-0/+3
| | | | | | | | | | | | | The erratum NMG_LBC103 is LBIU3 in MPC8548 errata document. Any local bus transaction may fail during LBIU resynchronization process when the clock divider [CLKDIV] is changing. Ensure there is no transaction on the local bus for at least 100 microseconds after changing clock divider LCRR[CLKDIV]. Refer to the erratum LBIU3 of mpc8548. Signed-off-by: Zhao Chenhui <chenhui.zhao@freescale.com> Signed-off-by: Kumar Gala <galak@kernel.crashing.org>
* powerpc/p4080: Add support for secure boot flowRuchika Gupta2011-10-03-1/+10
| | | | | | | | | | | | | | | | | | | | | | | | | Pre u-boot Flow: 1. User loads the u-boot image in flash 2. PBL/Configuration word is used to create LAW for Flash at 0xc0000000 (Please note that ISBC expects all these addresses, images to be validated, entry point etc within 0 - 3.5G range) 3. ISBC validates the u-boot image, and passes control to u-boot at 0xcffffffc. Changes in u-boot: 1. Temporarily map CONFIG_SYS_MONITOR_BASE to the 1M CONFIG_SYS_PBI_FLASH_WINDOW in AS=1. (The CONFIG_SYS_PBI_FLASH_WINDOW is the address map for the flash created by PBL/configuration word within 0 - 3.5G memory range. The u-boot image at this address has been validated by ISBC code) 2. Remove TLB entries for 0 - 3.5G created by ISBC code 3. Remove the LAW entry for the CONFIG_SYS_PBI_FLASH_WINDOW created by PBL/configuration word after switch to AS = 1 Signed-off-by: Ruchika Gupta <ruchika.gupta@freescale.com> Signed-off-by: Kuldip Giroh <kuldip.giroh@freescale.com> Acked-by: Wood Scott-B07421 <B07421@freescale.com> Signed-off-by: Kumar Gala <galak@kernel.crashing.org>
* powerpc/85xx: Add support for FMan ethernet in Independent modeKumar Gala2011-09-29-0/+5
| | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | The Frame Manager (FMan) on QorIQ SoCs with DPAA (datapath acceleration architecture) is the ethernet contoller block. Normally it is utilized via Queue Manager (Qman) and Buffer Manager (Bman). However for boot usage the FMan supports a mode similar to QE or CPM ethernet collers called Independent mode. Additionally the FMan block supports multiple 1g and 10g interfaces as a single entity in the system rather than each controller being managed uniquely. This means we have to initialize all of Fman regardless of the number of interfaces we utilize. Different SoCs support different combinations of the number of FMan as well as the number of 1g & 10g interfaces support per Fman. We add support for the following SoCs: * P1023 - 1 Fman, 2x1g * P4080 - 2 Fman, each Fman has 4x1g and 1x10g * P204x/P3041/P5020 - 1 Fman, 5x1g, 1x10g Signed-off-by: Dave Liu <daveliu@freescale.com> Signed-off-by: Andy Fleming <afleming@freescale.com> Signed-off-by: Timur Tabi <timur@freescale.com> Signed-off-by: Roy Zang <tie-fei.zang@freescale.com> Signed-off-by: Dai Haruki <dai.haruki@freescale.com> Signed-off-by: Kim Phillips <kim.phillips@freescale.com> Signed-off-by: Ioana Radulescu <ruxandra.radulescu@freescale.com> Signed-off-by: Lei Xu <B33228@freescale.com> Signed-off-by: Mingkai Hu <Mingkai.hu@freescale.com> Signed-off-by: Scott Wood <scottwood@freescale.com> Signed-off-by: Shaohui Xie <b21989@freescale.com> Signed-off-by: Kumar Gala <galak@kernel.crashing.org>
* powerpc/85xx: Handle the lack of L2 cache on P2040/P2040EKumar Gala2011-07-29-0/+8
| | | | | | | | | | The P2040/P2040E have no L2 cache. So we utilize the SVR to determine if we are one of these devices and skip the L2 init code in cpu_init.c and release. For the device tree we skip the updating of the L2 cache properties but we still update the chain of caches so the CPC/L3 node can be properly updated. Signed-off-by: Kumar Gala <galak@kernel.crashing.org>
* powerpc/85xx: Adding configuration for DCSRCR to enable 32M accessStephen George2011-07-29-0/+11
| | | | | | | | | | | | | | | Configuring DCSRCR to define the DCSR space to be 1G instead of the default 4M. DCSRCR only allows selection of either 4M or 1G. Most DCSR registers are within 4M but the Nexus trace buffer is located at offset 16M within the DCSR. Configuring the LAW to be 32M to allow access to the Nexus trace buffer. No TLB modification is required since accessing the Nexus trace buffer from within u-boot is not required. Signed-off-by: Stephen George <stephen.george@freescale.com> Signed-off-by: Kumar Gala <galak@kernel.crashing.org>
* powerpc/85xx: Enable Internal USB PHY for p2040, p3041, p5010 and p5020Roy Zang2011-04-27-0/+17
| | | | | | | | The P2040, P3041, P5010, and P5020 all have internal USB PHYs that we need to enable for them to function. Signed-off-by: Roy Zang <tie-fei.zang@freescale.com> Signed-off-by: Kumar Gala <galak@kernel.crashing.org>
* powerpc/85xx: Add PBL boot from SPI flash support on P4080DSShaohui Xie2011-04-10-0/+19
| | | | | | | | | | | | | PBL(pre-boot loader): SPI flash used as RCW(Reset Configuration Word) and PBI(pre-boot initialization) source, CPC(CoreNet Platform Cache) used as 1M SRAM where PBL will copy whole U-BOOT image to, U-boot can boot from CPC after PBL completes RCW and PBI phases. Signed-off-by: Chunhe Lan <b25806@freescale.com> Signed-off-by: Mingkai Hu <Mingkai.hu@freescale.com> Signed-off-by: Shaohui Xie <b21989@freescale.com> Signed-off-by: Roy Zang <tie-fei.zang@freescale.com> Signed-off-by: Kumar Gala <galak@kernel.crashing.org>
* powerpc/85xx: load ucode from nand flash before qe_initHaiying Wang2011-04-04-0/+17
| | | | | | | | In the case the QE's microcode is stored in nand flash, we need to load it from NAND flash to ddr first then the qe_init can get the ucode correctly. Signed-off-by: Haiying Wang <Haiying.Wang@freescale.com> Signed-off-by: Kumar Gala <galak@kernel.crashing.org>
* powerpc: Add cpu_secondary_init_r to allow for initialization post env setupKumar Gala2011-04-04-6/+9
| | | | | | | | | | | | | We can simplify some cpu/SoC level initialization by moving it to be after the environment and non-volatile storage is setup as there might be dependancies on such things in various boot configurations. For example for FSL SoC's with QE if we boot from NAND we need it setup to extra the ucode image to initialize the QE. If we always do this after environment & non-volatile storage is working we can have the code be the same regardless of NOR, NAND, SPI, MMC boot. Signed-off-by: Kumar Gala <galak@kernel.crashing.org>
* powerpc/85xx: Add the workaround for erratum CPC-A003 (enable on P4080)Kumar Gala2011-01-14-0/+3
| | | | | | | CoreNet Platform Cache single-bit data error scrubbing will cause data corruption. Disable the feature to workaround the issue. Signed-off-by: Kumar Gala <galak@kernel.crashing.org>
* powerpc/85xx: Add the workaround for erratum CPC-A002 (enable on P4080)Kumar Gala2011-01-14-0/+4
| | | | | | | CoreNet Platform Cache single-bit tag error scrubbing will cause tag corruption. Disable the feature to workaround the issue. Signed-off-by: Kumar Gala <galak@kernel.crashing.org>
* fsl_esdhc: Add the workaround for erratum ESDHC136 (enable on P4080)Roy Zang2011-01-14-0/+8
| | | | | | | | | | False multi-bit ECC errors will be reported by the eSDHC buffer which can trigger a reset request. We disable all ECC error checking on SDHC. Signed-off-by: Roy Zang <tie-fei.zang@freescale.com> Signed-off-by: Kumar Gala <galak@kernel.crashing.org>
* powerpc/8xxx: Refactor SRIO initialization into common codeKumar Gala2011-01-14-1/+7
| | | | | | | | | | | | | | | | | | | | | | | | | | | | Moved the SRIO init out of corenet_ds and into common code for 8xxx/QorIQ processors that have SRIO. We mimic what we do with PCIe controllers for SRIO. We utilize the fact that SRIO is over serdes to determine if its configured or not and thus can setup the LAWs needed for it dynamically. We additionally update the device tree (to remove the SRIO nodes) if the board doesn't have SRIO enabled. Introduced the following standard defines for board config.h: CONFIG_SYS_SRIO - Chip has SRIO or not CONFIG_SRIO1 - Board has SRIO 1 port available CONFIG_SRIO2 - Board has SRIO 2 port available (where 'n' is the port #) CONFIG_SYS_SRIOn_MEM_VIRT - virtual address in u-boot CONFIG_SYS_SRIOn_MEM_PHYS - physical address (for law setup) CONFIG_SYS_SRIOn_MEM_SIZE - size of window (for law setup) [ These mimic what we have for PCI and PCIe controllers ] Signed-off-by: Kumar Gala <galak@kernel.crashing.org> Acked-by: Wolfgang Denk <wd@denx.de>
* powerpc/85xx: Replace CONFIG_SYS_HAS_SERDES with a weak functionKumar Gala2011-01-14-2/+6
| | | | | | Instead of a #define use a null weak function for fsl_serdes_init Signed-off-by: Kumar Gala <galak@kernel.crashing.org>
* powerpc/85xx: do not reloc l2srbar if CONFIG_FLASH_BASE is not definedHaiying Wang2010-12-01-1/+1
| | | | | | | | This fixes the compiling error for the board which doesn't have NOR flash (so CONFIG_FLASH_BASE is not defined) Signed-off-by: Haiying Wang <Haiying.Wang@freescale.com> Signed-off-by: Kumar Gala <galak@kernel.crashing.org>
* powerpc/8xxx: share PIC defines among 85xx and 86xxKim Phillips2010-08-19-1/+1
| | | | | | | | | | fixes breakeage introduced by commit a37c36f4e70bada297f281b0e542539ad43e50f6 "powerpc/8xxx: query feature reporting register for num cores on unknown cpus" Reported-by: Wolfgang Denk <wd@denx.de> Signed-off-by: Kim Phillips <kim.phillips@freescale.com> Signed-off-by: Kumar Gala <galak@kernel.crashing.org>
* powerpc/p4080: Add workaround for erratum CPU22Kumar Gala2010-07-26-0/+7
| | | | Signed-off-by: Kumar Gala <galak@kernel.crashing.org>
* powerpc/p4080: Add support for CPC(Corenet platform cache) on CoreNet platformsKumar Gala2010-07-26-1/+44
| | | | | | | | | | | | | The CoreNet style platforms can have a L3 cache that fronts the memory controllers. Enable that cache as well as add information into the device tree about it. Signed-off-by: Kumar Gala <galak@kernel.crashing.org> Signed-off-by: Dave Liu <daveliu@freescale.com> Signed-off-by: Becky Bruce <beckyb@kernel.crashing.org> Signed-off-by: Roy Zang <tie-fei.zang@freescale.com> Signed-off-by: Timur Tabi <timur@freescale.com> Signed-off-by: Kumar Gala <galak@kernel.crashing.org>
* powerpc/85xx: Rework MPC8536 SERDES is_serdes_configured supportKumar Gala2010-07-21-7/+5
| | | | | | | | | | Move serdes init until after we are in ram so we can keep track of a global static protocal map for the particular serdes config we are in. This makes is_serdes_configured() much simplier and not constantly reading registers to determine if a given device is enabled based on the protocol. Signed-off-by: Kumar Gala <galak@kernel.crashing.org>
* 83xx/85xx/86xx: LBC register cleanupBecky Bruce2010-07-16-56/+2
| | | | | | | | | | | | | | | | | | | | | Currently, 83xx, 86xx, and 85xx have a lot of duplicated code dedicated to defining and manipulating the LBC registers. Merge this into a single spot. To do this, we have to decide on a common name for the data structure that holds the lbc registers - it will now be known as fsl_lbc_t, and we adopt a common name for the immap layouts that include the lbc - this was previously known as either im_lbc or lbus; use the former. In addition, create accessors for the BR/OR regs that use in/out_be32 and use those instead of the mismash of access methods currently in play. I have done a successful ppc build all and tested a board or two from each processor family. Signed-off-by: Becky Bruce <beckyb@kernel.crashing.org> Acked-by: Kim Phillips <kim.phillips@freescale.com> Signed-off-by: Kumar Gala <galak@kernel.crashing.org>
* 85xx/fsl-sata: Use is_serdes_configured() to determine if SATA is enabledKumar Gala2010-05-12-1/+13
| | | | | | | | | | | | On the MPC85xx platform if we have SATA its connected on SERDES. Determing if SATA is enabled via sata_initialize should not be board specific and thus we move it out of the MPC8536DS board code. Additionally, now that we have is_serdes_configured() we can determine if the given SATA port is enabled and error out if its not in the driver. Signed-off-by: Kumar Gala <galak@kernel.crashing.org>
* mpc85xx: Add the ability to set LCRR[CLKDIV] to improve R/W speed of flashLan Chunhe2010-04-26-0/+15
| | | | | | Signed-off-by: Lan Chunhe <b25806@freescale.com> Signed-off-by: Roy Zang <tie-fei.zang@freescale.com> Signed-off-by: Kumar Gala <galak@kernel.crashing.org>
* 85xx: Convert cpu_init_f code to use out_be32 for LBC registersKumar Gala2010-04-26-18/+18
| | | | Signed-off-by: Kumar Gala <galak@kernel.crashing.org>
* Move arch/ppc to arch/powerpcStefan Roese2010-04-21-0/+405
As discussed on the list, move "arch/ppc" to "arch/powerpc" to better match the Linux directory structure. Please note that this patch also changes the "ppc" target in MAKEALL to "powerpc" to match this new infrastructure. But "ppc" is kept as an alias for now, to not break compatibility with scripts using this name. Signed-off-by: Stefan Roese <sr@denx.de> Acked-by: Wolfgang Denk <wd@denx.de> Acked-by: Detlev Zundel <dzu@denx.de> Acked-by: Kim Phillips <kim.phillips@freescale.com> Cc: Peter Tyser <ptyser@xes-inc.com> Cc: Anatolij Gustschin <agust@denx.de>
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