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authorKumar Gala <galak@kernel.crashing.org>2010-05-05 22:35:27 -0500
committerKumar Gala <galak@kernel.crashing.org>2010-07-26 13:07:57 -0500
commitfd3c9befa83eecf6e7c6ef03c501159fbf754143 (patch)
tree825bcfea93aea0ed8d270bd993262bab45982981 /arch/powerpc/cpu/mpc85xx/cpu_init.c
parent61054ffa1690b2aef4e845c6aa071840b93abff6 (diff)
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powerpc/p4080: Add workaround for erratum CPU22
Signed-off-by: Kumar Gala <galak@kernel.crashing.org>
Diffstat (limited to 'arch/powerpc/cpu/mpc85xx/cpu_init.c')
-rw-r--r--arch/powerpc/cpu/mpc85xx/cpu_init.c7
1 files changed, 7 insertions, 0 deletions
diff --git a/arch/powerpc/cpu/mpc85xx/cpu_init.c b/arch/powerpc/cpu/mpc85xx/cpu_init.c
index a90ebb1..2c3be6d 100644
--- a/arch/powerpc/cpu/mpc85xx/cpu_init.c
+++ b/arch/powerpc/cpu/mpc85xx/cpu_init.c
@@ -32,6 +32,7 @@
#include <ioports.h>
#include <sata.h>
#include <asm/io.h>
+#include <asm/cache.h>
#include <asm/mmu.h>
#include <asm/fsl_law.h>
#include <asm/fsl_serdes.h>
@@ -245,6 +246,12 @@ int cpu_init_r(void)
volatile fsl_lbc_t *lbc = LBC_BASE_ADDR;
#endif
+#if defined(CONFIG_SYS_P4080_ERRATUM_CPU22)
+ flush_dcache();
+ mtspr(L1CSR2, (mfspr(L1CSR2) | L1CSR2_DCWS));
+ sync();
+#endif
+
puts ("L2: ");
#if defined(CONFIG_L2_CACHE)