Commit message (Expand) | Author | Age | Lines | |
---|---|---|---|---|
* | MIPS: L2 cache support | Paul Burton | 2016-09-21 | -1/+61 |
* | MIPS: Probe cache line sizes once during boot | Paul Burton | 2016-09-21 | -18/+25 |
* | MIPS: Fix invalidate_dcache_range to operate on L1 Dcache | Paul Burton | 2016-06-10 | -1/+1 |
* | MIPS: Abstract cache op loops with a macro | Paul Burton | 2016-05-31 | -41/+18 |
* | MIPS: Split I & D cache line size config | Paul Burton | 2016-05-31 | -15/+7 |
* | MIPS: Move cache sizes to Kconfig | Paul Burton | 2016-05-31 | -1/+1 |
* | mips: cache: Bulletproof the code against cornercases | Marek Vasut | 2016-02-01 | -0/+8 |
* | MIPS: sync processor and register definitions with linux-4.4 | Daniel Schwierzeck | 2016-01-16 | -2/+2 |
* | MIPS: unify cache maintenance functions | Paul Burton | 2015-01-29 | -0/+118 |