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* omap3: Reboot mode supportPaul Kocialkowski2015-08-12-0/+7
| | | | | | | | | | | | | | Reboot mode is written in scratchpad memory before reboot in the form of a single char, that is the first letter of the reboot mode string as passed to the reboot function. This mechanism is supported on OMAP3 both my the upstream kernel and by various TI kernels. It is up to each board to make use of this mechanism or not. Signed-off-by: Paul Kocialkowski <contact@paulk.fr> Reviewed-by: Tom Rini <trini@konsulko.com>
* nand: lpc32xx: add SLC NAND controller supportVladimir Zapolskiy2015-08-12-0/+3
| | | | | | | | | | | | | | | | | | | | | The change adds support of LPC32xx SLC NAND controller. LPC32xx SoC has two different mutually exclusive NAND controllers to communicate with single and multiple layer chips. This simple driver allows to specify NAND chip timings and defines custom read_buf()/write_buf() operations, because access to 8-bit data register must be 32-bit aligned. Support of hardware ECC calculation is not implemented (data correction is always done by software), since it requires a working DMA engine. The driver can be included to an SPL image. Signed-off-by: Vladimir Zapolskiy <vz@mleia.com> Acked-by: Scott Wood <scottwood@freescale.com> Tested-by: Sylvain Lemieux <slemieux@tycoint.com>
* arm: bcmcygnus: Enable Ethernet supportJiandong Zheng2015-08-12-0/+11
| | | | | | | | Enable BCM SF2 ethernet and PHY for BCM Cygnus SoC Signed-off-by: Jiandong Zheng <jdzheng@broadcom.com> Signed-off-by: Steve Rae <srae@broadcom.com> Acked-by: Joe Hershberger <joe.hershberger@ni.com>
* arm, at91: support for sam9260 based smartweb boardHeiko Schocher2015-08-12-0/+1
| | | | | | | | | | | | | | | | | | | | | | | | | | | | | add support for the at91sam9260 based board smartweb from siemens. SPL is used without serial support, as this SoC has only 4k sram for running SPL. Here a U-Boot bootlog: RomBOOT > U-Boot 2015.07-rc2-00109-g4ae828c (Jun 15 2015 - 09:31:16 +0200) CPU: AT91SAM9260 Crystal frequency: 18.432 MHz CPU clock : 198.656 MHz Master clock : 99.328 MHz Watchdog enabled DRAM: 64 MiB WARNING: Caches not enabled NAND: 256 MiB In: serial Out: serial Err: serial Net: macb0 Hit any key to stop autoboot: 0 U-Boot> Signed-off-by: Heiko Schocher <hs@denx.de>
* sunxi: display: Add a few extra register and constant definesHans de Goede2015-08-08-6/+42
| | | | | | | | | | | | | Add a few extra sunxi display registers and constant defines. Also rename some existing defines (e.g. dropping _GCTRL) and make some more generic (e.g. dropping the 2x scaling from SUNXI_LCDC_TCON1_TIMING_V_TOTAL). This is a preparation patch for adding composite video out support. Signed-off-by: Hans de Goede <hdegoede@redhat.com> Acked-by: Ian Campbell <ijc@hellion.org.uk>
* sunxi: usb-phy: Never power off the usb portsHans de Goede2015-08-08-0/+1
| | | | | | | | | | | | | | | | | | | | | USB devices are not really designed to get the power bounced off and on at them. Esp. USB powered harddisks do not like this. Currently we power off the USB ports both on a "usb reset" and when booting the kernel, causing the usb-power to bounce off and then back on again. This patch removes the powering off calls, fixing the undesirable power bouncing. Note this requires some special handling for the OTG port: 1) We must skip the external vbus check if we've already enabled our own vbus to avoid false positives 2) If on an usb reset we no longer detect that the id-pin is grounded, turn off vbus as that means an external vbus may be present now Signed-off-by: Hans de Goede <hdegoede@redhat.com> Acked-by: Ian Campbell <ijc@hellion.org.uk>
* sunxi: nand: Add pinmux and clock settings for NAND supportKarol Gugala2015-08-08-0/+3
| | | | | | | | | | To enable NAND flash in sunxi SPL, pins 0-6, 8-22 and 24 on port C are configured. Signed-off-by: Karol Gugala <kgugala@antmicro.com> Signed-off-by: Piotr Zierhoffer <pzierhoffer@antmicro.com> Acked-by: Hans de Goede <hdegoede@redhat.com> Signed-off-by: Hans de Goede <hdegoede@redhat.com>
* Merge git://git.denx.de/u-boot-dmTom Rini2015-08-06-2/+1
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| * exynos: video: Remove non-device-tree codeSimon Glass2015-08-05-2/+0
| | | | | | | | | | | | We always use device tree on exynos, so remove the unused code. Signed-off-by: Simon Glass <sjg@chromium.org>
| * exynos: Add support for the DisplayPort hotplug detectSimon Glass2015-08-05-0/+1
| | | | | | | | | | | | Allow this function to be selected using the pinmux API. Signed-off-by: Simon Glass <sjg@chromium.org>
* | ARM: tegra: enable GPU DT node when appropriateAlexandre Courbot2015-08-06-0/+15
| | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | T124/210 requires some specific configuration (VPR setup) to be performed by the bootloader before the GPU can be used. For this reason, the GPU node in the device tree is disabled by default. This patch enables the node if U-boot has performed VPR configuration. Boards enabled by this patch are T124's Jetson TK1 and Venice2 and T210's P2571. Signed-off-by: Alexandre Courbot <acourbot@nvidia.com> Cc: Stephen Warren <swarren@nvidia.com> Cc: Tom Warren <twarren@nvidia.com> Signed-off-by: Tom Warren <twarren@nvidia.com>
* | ARM: tegra: move VPR configuration to a later stageAlexandre Courbot2015-08-06-9/+27
| | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | U-boot is responsible for enabling the GPU DT node after all necessary configuration (VPR setup for T124) is performed. In order to be able to check whether this configuration has been performed right before booting the kernel, make it happen during board_init(). Also move VPR configuration into the more generic gpu.c file, which will also host other GPU-related functions, and let boards specify individually whether they need VPR setup or not. Signed-off-by: Alexandre Courbot <acourbot@nvidia.com> Cc: Stephen Warren <swarren@nvidia.com> Cc: Tom Warren <twarren@nvidia.com> Signed-off-by: Tom Warren <twarren@nvidia.com>
* | Tegra: PLL: use per-SoC pllinfo table instead of PLL_DIVM/N/P, etc.Tom Warren2015-08-05-29/+25
| | | | | | | | | | | | | | | | | | | | | | | | | | Added PLL variables (dividers mask/shift, lock enable/detect, etc.) to new pllinfo struct for each Soc/PLL. PLLA/C/D/E/M/P/U/X. Used pllinfo struct in all clock functions, validated on T210. Should be equivalent to prior code on T124/114/30/20. Thanks to Marcel Ziswiler for corrections to the T20/T30 values. Signed-off-by: Marcel Ziswiler <marcel.ziswiler@toradex.com> Tested-by: Marcel Ziswiler <marcel.ziswiler@toradex.com> Signed-off-by: Tom Warren <twarren@nvidia.com>
* | Tegra: clocks: Add 38.4MHz OSC support for T210 useTom Warren2015-08-05-0/+2
|/ | | | | | | | | | | | | | | Added 38.4MHz/48MHz entries to pll_x_table for CPU PLL. Needs to be measured - should be close to 700MHz (1.4G/2). Note that some freqs aren't in the PLLU table in T210 TRM (13, 26MHz), so I used the 12MHz table entry for them. They shouldn't be selected since they're not viable T210 OSC freqs. Since there are now 2 new OSC defines, all tables (pll_x_table, PLLU) had to increase by two entries, but since 38.4/48MHz are not viable osc freqs on T20/30/114, etc, they're just set to 0. Signed-off-by: Tom Warren <twarren@nvidia.com>
* usb: musb-new: CONFIG_MUSB prefix replacement with CONFIG_USB_MUSBPaul Kocialkowski2015-08-05-1/+1
| | | | | | | | | USB-related options are usually prefixed with CONFIG_USB and platform-specific adaptation for the MUSB controller already have a CONFIG_USB_MUSB prefix, so this switches all MUSB-related options to a CONFIG_USB_MUSB prefix, for consistency. Signed-off-by: Paul Kocialkowski <contact@paulk.fr>
* armv8/lsch3/config: Define USB XHCI controller base address for LS2085ANikhil Badola2015-08-03-0/+3
| | | | | | | | Define base address of both usb xhci controllers in lsch3 config in the format (IMMR + offset) for LS2085A Signed-off-by: Nikhil Badola <nikhil.badola@freescale.com> Reviewed-by: York Sun <yorksun@freescale.com>
* armv8/lsch3/config: Define CONFIG_SYS_CACHELINE_SIZE for LS2085ANikhil Badola2015-08-03-0/+1
| | | | | | | | Define CONFIG_SYS_CACHELINE_SIZE for LS2085A which is required by USB XHCI stack for alignment Signed-off-by: Nikhil Badola <nikhil.badola@freescale.com> Reviewed-by: York Sun <yorksun@freescale.com>
* Merge branch 'master' of git://www.denx.de/git/u-boot-imxTom Rini2015-08-02-97/+1381
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| * imx:mx6ul add dram spl configuration and header filePeng Fan2015-08-02-0/+90
| | | | | | | | | | | | | | | | | | | | | | | | 1. Define two structures mx6ul_iomux_ddr_regs and mx6ul_iomux_grp_regs. 2. Add a new function mx6ul_dram_iocfg to configure dram io. 3. Refactor MMDC1 macro, discard "#ifdef CONFIG_MX6SX". Since only mmdc0 channel exists on i.MX6SX/UL, redefine MMDC1 macro support runtime check, but not hardcoding #ifdef macros. 4. Introduce mx6ul-ddr.h, which includes the register address for DRAM IO configuration. Signed-off-by: Peng Fan <Peng.Fan@freescale.com>
| * imx: mx6 add PAD_CTL_SPEED_LOW for i.MX6SX/ULPeng Fan2015-08-02-0/+4
| | | | | | | | | | | | | | PAD_CTL_SPEED_LOW for i.MX6SX/UL is (0 << 6) Signed-off-by: Ye.Li <B37916@freescale.com> Signed-off-by: Peng Fan <Peng.Fan@freescale.com>
| * imx:mx6ul add clock supportPeng Fan2015-08-02-31/+67
| | | | | | | | | | | | | | | | | | | | | | | | | | | | | | 1. Add enet, uart, i2c, ipg clock support for i.MX6UL. 2. Correct get_periph_clk, it should account for MXC_CCM_CBCDR_PERIPH_CLK2_PODF_MASK. 3. Refactor get_mmdc_ch0_clk to make all i.MX6 share one function, but not use 'ifdef'. 4. Use CONFIG_FSL_QSPI for enable_qspi_clk, but not #ifdef CONFIG_MX6SX. 5. Use CONFIG_PCIE_IMX for pcie clock settings, use CONFIG_CMD_SATA for sata clock settings. In this way, we not need "#if defined(CONFIG_MX6Q) || defined....", only need one CONFIG_PCIE_IMX in header file. Signed-off-by: Ye.Li <B37916@freescale.com> Signed-off-by: Peng Fan <Peng.Fan@freescale.com>
| * imx: mx6ul Add CONFIG_SYS_CACHELINE_SIZE for i.MX6ULPeng Fan2015-08-02-0/+4
| | | | | | | | | | | | | | Since i.MX6UL's cache line size is 64bytes, need to define the macro CONFIG_SYS_CACHELINE_SIZE to 64 for i.MX6UL. Signed-off-by: Peng Fan <Peng.Fan@freescale.com>
| * imx: mx6ul: Update imx registers head filePeng Fan2015-08-02-25/+35
| | | | | | | | | | | | | | | | | | | | | | | | 1. Update imx register base address for i.MX6UL. 2. Remove duplicated MXS_APBH/GPMI/BCH_BASE. 3. Remove #ifdef for register addresses that equal to "AIPS2_OFF_BASE_ADDR + 0x34000" for different chips. 4. According fuse map, complete fuse_bank4_regs. 5. Move AIPS3_ARB_BASE_ADDR and AIPS3_ARB_END_ADDR out of #ifdef CONFIG_MX6SX, because we can use runtime check Signed-off-by: Peng Fan <Peng.Fan@freescale.com>
| * imx: mx6ul: Add pins IOMUX head filePeng Fan2015-08-02-0/+1067
| | | | | | | | | | | | | | Add i.MX6UL pins IOMUX file which defines the IOMUX settings for choose. Signed-off-by: Peng Fan <Peng.Fan@freescale.com> Signed-off-by: Ye.Li <B37916@freescale.com>
| * imx: mx6ul: Add i.MX6UL CPU typePeng Fan2015-08-02-1/+2
| | | | | | | | | | | | | | | | | | | | Add MXC_CPU_MX6UL for i.MX6UL CPU type which is got at runtime from DIGPROG register. But the value has been occupied by MXC_CPU_MX6D which is not real id from DIGPROG register, so change i.MX6D to value 0x67 which was not occupied. Signed-off-by: Peng Fan <Peng.Fan@freescale.com> Signed-off-by: Ye.Li <B37916@freescale.com>
| * imx: mx6: ccm: Change the clock settings for i.MX6QPPeng Fan2015-08-02-23/+25
| | | | | | | | | | | | | | | | | | | | | | | | Since i.MX6QP changes some CCM registers, so modify the clocks settings to follow the hardware changes. In c files, use runtime check and discard #ifdef. Signed-off-by: Peng Fan <Peng.Fan@freescale.com> Signed-off-by: Ye.Li <B37916@freescale.com> Reviewed-by: Fabio Estevam <fabio.estevam@freescale.com> Acked-by: Stefano Babic <sbabic@denx.de>
| * imx: add cpu type for i.MX6QP/DPPeng Fan2015-08-02-3/+3
| | | | | | | | | | | | | | | | | | | | | | Add cpu type for i.MX6QP/DP. This patch also fix is_mx6dqp(), since get_cpu_rev can return MXC_CPU_MX6QP and MXC_CPU_MX6DP, we should use: (is_cpu_type(MXC_CPU_MX6QP) || is_cpu_type(MXC_CPU_MX6DP)). Signed-off-by: Peng Fan <Peng.Fan@freescale.com> Acked-by: Stefano Babic <sbabic@denx.de>
| * Merge branch 'master' of git://git.denx.de/u-bootStefano Babic2015-07-17-0/+26
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| * | i2c: fix vf610 supportAlbert ARIBAUD \(3ADEV\)2015-07-10-4/+15
| | | | | | | | | | | | | | | | | | | | | Add support in mxc_i2c driver, iomux_v3 and vf610 architecture for the four I2C instances available in VF610. Signed-off-by: Albert ARIBAUD (3ADEV) <albert.aribaud@3adev.fr>
| * | iMX: adding parsing to hab_status commandUlises Cardenas2015-07-10-12/+73
| | | | | | | | | | | | | | | | | | | | | | | | hab_status command returns a memory dump of the hab event log. But the raw data is not human-readable. Parsing such data into readable event will help to minimize debbuging time. Signed-off-by: Ulises Cardenas <Ulises.Cardenas@freescale.com>
| * | imx: mx6 add i2c4 clock support for i.MX6SXPeng Fan2015-07-10-3/+2
| | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | Add I2C4 clock support for i.MX6SX. Since we use runtime check, but not macro, we need to remove `#ifdef ..` in crm_regs.h, or gcc will fail to compile the code succesfully. Making the macros only for i.MX6SX open to other i.MX6x maybe not a good choice, but we have runtime check. Signed-off-by: Peng Fan <Peng.Fan@freescale.com>
| * | imx: mx6 remove duplicated enable_cspi_clockPeng Fan2015-07-10-1/+0
| | | | | | | | | | | | | | | | | | | | | | | | | | | | | | enable_spi_clock does the same thing with enable_cspi_clock, so remove enable_cspi_clock. Remove enable_cspi_clock prototype in header file convert cm_fx6/spl.c to use enable_spi_clk Signed-off-by: Peng Fan <Peng.Fan@freescale.com> Acked-by: Stefano Babic <sbabic@denx.de>
* | | armv8: caches: Added routine to set non cacheable regionSiva Durga Prasad Paladugu2015-07-31-10/+19
| | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | Added routine mmu_set_region_dcache_behaviour() to set a particular region as non cacheable. Define dummy routine for mmu_set_region_dcache_behaviour() to handle incase of dcache off. Signed-off-by: Siva Durga Prasad Paladugu <sivadur@xilinx.com> Acked-by: Michal Simek <michal.simek@xilinx.com>
* | | Merge branch 'master' of git://git.denx.de/u-boot-tegraTom Rini2015-07-29-14/+1330
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| * | | ARM: Tegra210: Add support to common Tegra source/config filesTom Warren2015-07-28-14/+45
| | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | Derived from Tegra124, modified as appropriate during T210 board bringup. Cleaned up debug statements to conserve string space, too. This also adds misc 64-bit changes from Thierry Reding/Stephen Warren. Signed-off-by: Tom Warren <twarren@nvidia.com> Signed-off-by: Thierry Reding <treding@nvidia.com> Signed-off-by: Stephen Warren <swarren@nvidia.com>
| * | | ARM: Tegra210: Add SoC code/include files for T210Tom Warren2015-07-28-0/+1285
| | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | All based off of Tegra124. As a Tegra210 board is brought up, these may change a bit to match the HW more closely, but probably 90% of this is identical to T124. Note that since T210 is a 64-bit build, it has no SPL component, and hence no cpu.c for Tegra210. Signed-off-by: Tom Warren <twarren@nvidia.com>
* | | | Merge branch 'zynq' of git://www.denx.de/git/u-boot-microblazeTom Rini2015-07-28-0/+22
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| * | | | ARM: zynqmp: Wire up SATA for the boardMichal Simek2015-07-28-0/+2
| | | | | | | | | | | | | | | | | | | | | | | | | | | | | | Enable SATA for the ZynqMP targets. Signed-off-by: Michal Simek <michal.simek@xilinx.com>
| * | | | ARM: zynqmp: Wire up ethernet controllersMichal Simek2015-07-28-0/+10
| | | | | | | | | | | | | | | | | | | | | | | | | | | | | | Wire up ethernet controllers and enable MII and BOOTP options. Signed-off-by: Michal Simek <michal.simek@xilinx.com>
| * | | | zynqmp: Add support for IP detection via SLCRMichal Simek2015-07-28-0/+10
| |/ / / | | | | | | | | | | | | | | | | | | | | | | | | SLCR can be used for IP configuration setting. Add SLCR skeleton to enable run time checking. Signed-off-by: Michal Simek <michal.simek@xilinx.com>
* | | | stm32f429: pass the device unique ID in DTBAntonio Borneo2015-07-27-0/+10
| | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | Read device unique ID and set environment variable "serial#". Value would then be passed to kernel through DTB. To read ID from DTB, kernel is required to have commit: 3f599875e5202986b350618a617527ab441bf206 (ARM: 8355/1: arch: Show the serial number from devicetree in cpuinfo) This commit is already mainline since v4.1-rc1. Signed-off-by: Antonio Borneo <borneo.antonio@gmail.com> To: Albert Aribaud <albert.u.boot@aribaud.net> To: Tom Rini <trini@konsulko.com> To: Kamil Lulko <rev13@wp.pl> Cc: u-boot@lists.denx.de
* | | | omap3: Definitions for SYS_BOOT-based fallback boot device selectionPaul Kocialkowski2015-07-27-1/+0
| | | | | | | | | | | | | | | | | | | | | | | | | | | | This introduces code to read the value of the SYS_BOOT pins on the OMAP3, as well as the memory-preferred scheme for the interpretation of each value. Signed-off-by: Paul Kocialkowski <contact@paulk.fr>
* | | | omap-common: SYS_BOOT-based fallback boot device selection for peripheral bootPaul Kocialkowski2015-07-27-0/+4
| | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | OMAP devices might boot from peripheral devices, such as UART or USB. When that happens, the U-Boot SPL tries to boot the next stage (complete U-Boot) from that peripheral device, but in most cases, this is not a valid boot device. This introduces a fallback option that reads the SYS_BOOT pins, that are used by the bootrom to determine which device to boot from. It is intended for the SYS_BOOT value to be interpreted in the memory-preferred scheme, so that the U-Boot SPL can load the next stage from a valid location. Practically, this options allows loading the U-Boot SPL through USB and have it load the next stage according to the memory device selected by SYS_BOOT instead of stalling. Signed-off-by: Paul Kocialkowski <contact@paulk.fr>
* | | | omap: SPL boot devices cleanup and completionPaul Kocialkowski2015-07-27-67/+88
| | | | | | | | | | | | | | | | | | | | | | | | | | | | This cleans up the SPL boot devices for omap platforms and introduces support for missing boot devices. Signed-off-by: Paul Kocialkowski <contact@paulk.fr>
* | | | omap-common: Common boot code OMAP3 support and cleanupPaul Kocialkowski2015-07-27-42/+63
|/ / / | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | This introduces OMAP3 support for the common omap boot code, as well as a major cleanup of the common omap boot code. First, the omap_boot_parameters structure becomes platform-specific, since its definition differs a bit across omap platforms. The offsets are removed as well since it is U-Boot's coding style to use structures for mapping such kind of data (in the sense that it is similar to registers). It is correct to assume that romcode structure encoding is the same as U-Boot, given the description of these structures in the TRMs. The original address provided by the bootrom is passed to the U-Boot binary instead of a duplicate of the structure stored in global data. This allows to have only the relevant (boot device and mode) information stored in global data. It is also expected that the address where the bootrom stores that information is not overridden by the U-Boot SPL or U-Boot. The save_omap_boot_params is expected to handle all special cases where the data provided by the bootrom cannot be used as-is, so that spl_boot_device and spl_boot_mode only return the data from global data. All of this is only relevant when the U-Boot SPL is used. In cases it is not, save_boot_params should fallback to its weak (or board-specific) definition. save_omap_boot_params should not be called in that context either. Signed-off-by: Paul Kocialkowski <contact@paulk.fr>
* | | Merge branch 'master' of http://git.denx.de/u-boot-sunxiTom Rini2015-07-25-0/+9
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| * | | sunxi: musb: Move musb config and platdata to the sunxi-musb glueHans de Goede2015-07-25-0/+7
| | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | Move the musb config and platdata to the sunxi-musb glue, which is where it really belongs. This is preparation patch for adding device-model support for the sunxi-musb-host code. Signed-off-by: Hans de Goede <hdegoede@redhat.com> Acked-by: Ian Campbell <ijc@hellion.org.uk>
| * | | sunxi: usb-phy: Add support for reading otg id pin valueHans de Goede2015-07-25-0/+1
| | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | Add support for reading the id pin value of the otg connector to the usb phy code. Signed-off-by: Hans de Goede <hdegoede@redhat.com> Acked-by: Ian Campbell <ijc@hellion.org.uk>
| * | | sunxi: Create helper function veryfing valid boot signature on MMCDaniel Kochmański2015-07-24-0/+1
| | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | This patch extracts checking for valid SD card "eGON.BT0" signature from `board_mmc_init` into function `sunxi_mmc_has_egon_boot_signature`. Buffer for mmc sector is allocated and freed at runtime. `panic` is triggered on malloc failure. Signed-off-by: Daniel Kochmański <dkochmanski@turtle-solutions.eu> CC: Roy Spliet <r.spliet@ultimaker.com> Cc: Ian Campbell <ijc@hellion.org.uk> [hdegoede@redhat.com: Small bugfix to make it work for devs other then mmc0] Acked-by: Hans de Goede <hdegoede@redhat.com> Signed-off-by: Hans de Goede <hdegoede@redhat.com>
* | | | usb: gadget: bcm_udc_otg filesJiandong Zheng2015-07-22-0/+7
| | | | | | | | | | | | | | | | | | | | | | | | | | | | Add the required files for the Broadcom UDC OTG interface. Signed-off-by: Jiandong Zheng <jdzheng@broadcom.com> Signed-off-by: Steve Rae <srae@broadcom.com>
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