Commit message (Expand) | Author | Age | Lines | |
---|---|---|---|---|
* | tegra: Correct PLL access in ap20.c and clock.c | Simon Glass | 2012-07-07 | -2/+3 |
* | tegra: Add functions to access low-level Osc/PLL details | Simon Glass | 2012-05-15 | -0/+22 |
* | tegra: fdt: Add function to return peripheral/clock ID | Simon Glass | 2012-03-29 | -0/+13 |
* | tegra: add clock_ll_start_uart() to enable UART prior to reloc | Simon Glass | 2011-12-24 | -0/+11 |
* | tegra2: Add more clock functions | Simon Glass | 2011-10-27 | -5/+103 |
* | tegra2: Rename CLOCK_PLL_ID to CLOCK_ID | Simon Glass | 2011-10-27 | -22/+21 |
* | Tegra2: Add more clock support | Simon Glass | 2011-09-04 | -0/+263 |