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* MLK-10774-1 imx: LDO: add LDO bypassPeng Fan2015-04-29-0/+142
| | | | | | | | | | | | | | | | | | | | | | | | This patch is from two commits: 1. 748eac71fde78aa0c2e8cb3a3bab94bd994c06f5 ENGR00315499-5: Support i.MX6 1.2GHz via LDO bypass Add check for 1.2GHz core speed. If Speed grading fuse is for 1.2GHz, enable LDO bypass and setup PMIC voltages. LDO bypass is dependent on the flatten device tree file. 2. 93d457e4c601ee5266bc30b7dfa5fa1bbfa8500a MLK-9891-1: ARM: imx6: split WDOG_B setting from set_anatop_bypass() function We set WDOG_B in set_anatop_bypass() before, because it is the only case, but now on i.mx6sabreauto board, we didn't use ldo-bypass mode, but have to use WDOG_B to reboot whole board, so split these code to independent function so that board file can call it freely. Board code is not included, board ldo bypass code will be in bsp update code. Signed-off-by: Peng Fan <Peng.Fan@freescale.com>
* Merge branch 'master' of git://www.denx.de/git/u-boot-imxTom Rini2015-04-13-0/+27
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| * ARM: mx5: add support for USB armory boardAndrej Rosano2015-04-09-0/+11
| | | | | | | | | | | | | | | | | | | | | | | | | | | | | | Add support for Inverse Path USB armory board, an open source flash-drive sized computer based on Freescale i.MX53 SoC. http://inversepath.com/usbarmory Signed-off-by: Andrej Rosano <andrej@inversepath.com> Cc: Stefano Babic <sbabic@denx.de> Cc: Chris Kuethe <chris.kuethe@gmail.com> Cc: Fabio Estevam <festevam@gmail.com> Cc: Vagrant Cascadian <vagrant@debian.org> Tested-By: Vagrant Cascadian <vagrant@debian.org> Tested-by: Chris Kuethe <chris.kuethe@gmail.com>
| * ARM: mx5: move to a standard arch/board approachAndrej Rosano2015-04-09-0/+16
| | | | | | | | | | | | | | | | | | | | Move the MX5 based boards to arch/arm/cpu/armv7/mx5, following the commit: 89ebc82137bebb11a8191f8b9cbf08f2533ae8bc Signed-off-by: Andrej Rosano <andrej@inversepath.com> Cc: Stefano Babic <sbabic@denx.de> Cc: Vagrant Cascadian <vagrant@debian.org> Tested-by: Chris Kuethe <chris.kuethe@gmail.com>
* | arm: armada-xp: Fix SPL for AXP by using save_boot_params_retStefan Roese2015-04-11-1/+1
| | | | | | | | | | | | | | | | | | | | | | Patch e11c6c27 (arm: Allow lr to be saved by board code) introduced a different method to return from save_boot_params(). The SPL support for AXP has been pulled and changing to this new method is now required for SPL to work correctly. Signed-off-by: Stefan Roese <sr@denx.de> Cc: Simon Glass <sjg@chromium.org> Cc: Luka Perkov <luka.perkov@sartura.hr>
* | Merge branch 'u-boot/master'Albert ARIBAUD2015-04-10-51/+136
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| * | am33xx/ddr.c: Fix regression on DDR2 platformsTom Rini2015-04-07-1/+1
| | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | Back in fc46bae a "clean up" was introduced that intended to reconcile some of the AM335x codepaths based on how AM43xx operates. Unfortunately this introduced a regression on the DDR2 platforms. This was un-noticed on DDR3 (everything except for Beaglebone White) as we had already populated sdram_config correctly in sequence. This change brings us back to the older behavior and is fine on all platforms. Tested on Beaglebone White, Beaglebone Black and AM335x GP EVM Reported-by: Matt Ranostay <mranostay@gmail.com> Signed-off-by: Tom Rini <trini@konsulko.com>
| * | Exynos5: Fix rpll_sdiv to support both peach-pit and peach-pi panelsAjay Kumar2015-04-06-2/+2
| | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | The existing setting for rpll_sdiv generates 70.5Mhz RPLL video clock to drive 1366x768 panel on peach_pit. This clock rate is not sufficient to drive 1920x1080 panel on peach-pi. So, we adjust rpll_sdiv to 3 so that it generates 141Mhz pixel clock which can drive peach-pi LCD. This change doesn't break peach-pit LCD since 141/2=70.5Mhz, i.e FIMD divider at IP level will get set to 1(the required divider setting will be calculated and set by exynos_fimd_set_clock()) and hence peach-pit LCD still works fine. Signed-off-by: Ajay Kumar <ajaykumar.rs@samsung.com> Reviewed-by: Simon Glass <sjg@chromium.org> Tested-by: Simon Glass <sjg@chromium.org> Signed-off-by: Minkyu Kang <mk7.kang@samsung.com>
| * | arm: exynos: add display clocks for Exynos5800Ajay Kumar2015-04-06-3/+62
| | | | | | | | | | | | | | | | | | | | | | | | | | | | | | Add get_lcd_clk and set_lcd_clk callbacks for Exynos5800 needed by exynos video driver. Signed-off-by: Ajay Kumar <ajaykumar.rs@samsung.com> Reviewed-by: Simon Glass <sjg@chromium.org> Tested-by: Simon Glass <sjg@chromium.org> Signed-off-by: Minkyu Kang <mk7.kang@samsung.com>
| * | Exynos: Clock: Fix exynos5_get_periph_rate for I2C.Guillaume GARDET2015-04-06-2/+2
| | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | Commit 2e82e9252695a612ab0cbf40fa0c7368515f6506 'Exynos: Clock: Cleanup soc_get_periph_rate' introduced a bug in I2C config. This patch makes cros_ec keyboard working again on Samsung Chromebook (snow). Changes in V2: reorder lines as requested by Joonyoung Shim. Signed-off-by: Guillaume GARDET <guillaume.gardet@free.fr> Cc: Akshay Saraswat <akshay.s@samsung.com> Cc: Minkyu Kang <mk7.kang@samsung.com> Cc: Joonyoung Shim <jy0922.shim@samsung.com> Reviewed-by: Simon Glass <sjg@chroimum.org> Tested-by: Simon Glass <sjg@chroimum.org> Signed-off-by: Minkyu Kang <mk7.kang@samsung.com>
| * | Merge branch 'master' of git://git.denx.de/u-boot-imxTom Rini2015-03-31-0/+42
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| | * board/seco: Add mx6q-uq7 basic board supportBoris BREZILLON2015-03-23-0/+11
| | | | | | | | | | | | | | | | | | | | | | | | Add basic SECO MX6Q/uQ7 board support (Ethernet, UART, SD are supported). It also adds a Kconfig skeleton to later add more SECO board (supporting SoC and board variants). Signed-off-by: Boris Brezillon <boris.brezillon@free-electrons.com>
| | * ARM: mx6: move to a standard arch/board approachBoris BREZILLON2015-03-23-0/+31
| | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | Freescale boards are currently all defined in arch/arm/Kconfig, which makes them hard to detect. Moreover the MX6 SoC variant (Q, D, DL, S, SL) selection is currently done via the SYS_EXTRA_OPTIONS option which marked as deprecated. Move to a more standard way to select sub-architecture and board by creating a Kconfig under arch/arm/cpu/armv7/mx6 and a new ARCH_MX6 option. Existing MX6 board definitions should be moved in this new Kconfig in choice menu, and new boards should be directly declared in this menu. Signed-off-by: Boris Brezillon <boris.brezillon@free-electrons.com>
| * | sunxi: use CONFIG_SYS_CLK_FREQ to set cpu clockIain Paton2015-03-29-1/+1
| | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | make the CPU clock selectable via Kconfig this removes the sunxi specific CONFIG_CLK_FULL_SPEED defined in each soc header and replaces it's use in board/sunxi/board.c with CONFIG_SYS_CLK_FREQ from Kconfig which allows us to configure board specific frequency on boot Signed-off-by: Iain Paton <ipaton0@gmail.com> [hdegoede@redhat.com s/CONFIG_SYS_CLK_FREQ/CONFIG_TIMER_CLK_FREQ/ for the arch-timer clk speed on sun7i to fix mis-compile on sun7i] Acked-by: Hans de Goede <hdegoede@redhat.com> Signed-off-by: Hans de Goede <hdegoede@redhat.com>
| * | sunxi: sun4i: improve cpu clock selection methodIain Paton2015-03-29-16/+19
| | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | clock_set_pll1 would pick the next highest available cpu clock speed if a value not in the pre defined table was selected. this potentially results in overclocking the soc. reverse the selection method so that we select the next lowest speed and add the missing 912Mhz setting that's requested by sun7i which also uses the sun4i clock code. Signed-off-by: Iain Paton <ipaton0@gmail.com> Acked-by: Hans de Goede <hdegoede@redhat.com> Signed-off-by: Hans de Goede <hdegoede@redhat.com>
| * | sunxi: musb: Fix some lo speed devices not working with musb hostHans de Goede2015-03-29-0/+7
| | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | The usb0 / otg phy on sunxi boards has a bug where it wrongly detects a high speed squelch on usb reset deassert when a lo speed device is plugged in. The android kernel has a work around for this in the form of temporary disabling the phy's squelch detection on reset deassert, this commit adds the same workaround to the u-boot sunxi musb code, thereby fixing various usb lo speed devices not working. Tested with a (before non working) usb keyboard and a usb 2.4 GHz wireless keyboard/mouse combo receiver. Signed-off-by: Hans de Goede <hdegoede@redhat.com> Acked-by: Ian Campbell <ijc@hellion.org.uk>
| * | ARM: bcm283x: merge BCM2835/BCM2836 directories into mach-bcm283xMasahiro Yamada2015-03-28-14/+0
| | | | | | | | | | | | | | | | | | | | | | | | | | | | | | BCM2835 (used on Raspberry Pi) and BCM2836 (used on Raspberry Pi 2) are similar enough. One of the biggest differences is the ARM processor. It is reasonable to collect the source files into a single place, arch/arm/mach-bcm283x/. Signed-off-by: Masahiro Yamada <yamada.masahiro@socionext.com> Acked-by: Stephen Warren <swarren@wwwdotorg.org>
| * | malloc_f: enable SYS_MALLOC_F by default if DM is onMasahiro Yamada2015-03-28-6/+0
| | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | This option has a bool type, not hex. Fix it and enable it if CONFIG_DM is on because Driver Model always requires malloc memory. Devices are scanned twice, before/after relocation. CONFIG_SYS_MALLOC_F should be enabled to use malloc memory before relocation. As it is board-independent, handle it globally. Signed-off-by: Masahiro Yamada <yamada.masahiro@socionext.com> Acked-by: Stephen Warren <swarren@wwwdotorg.org> Reviewed-by: Simon Glass <sjg@chromium.org> Acked-by: Robert Baldyga <r.baldyga@samsung.com>
| * | malloc_f: remove redundant defalut values of CONFIG_SYS_MALLOC_F_LENMasahiro Yamada2015-03-28-6/+0
| | | | | | | | | | | | | | | | | | | | | | | | | | | | | | The default value of CONFIG_SYS_MALLOC_F_LEN is defined by ./Kconfig as 0x400. Each defconfig or Kconfig need not repeat the same value. Signed-off-by: Masahiro Yamada <yamada.masahiro@socionext.com> Acked-by: Stephen Warren <swarren@wwwdotorg.org> Reviewed-by: Simon Glass <sjg@chromium.org> Acked-by: Robert Baldyga <r.baldyga@samsung.com>
* | | ARM: move -march=* and -mtune= options to arch/arm/MakefileMasahiro Yamada2015-03-27-5/+0
|/ / | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | My main motivations for this commit are: [1] Follow the arch/arm/Makefile style of Linux Kernel [2] Maintain compiler options systematically Currently, we give -march=* and -mtune=* options inconsistently: Only some of the CPUs pass -march=* and -mtune=* options. By collecting such options into the single place arch/arm/Makefile we can tell which options are missing at a glance. [3] Prepare for deprecating arch/*/cpu/*/config.mk Note: This commit just moves the compiler options so as not to change the behavior at all. It does not care about the correctness of the given options. Fox example, "-march=armv5te" might be better than "-march=armv4" for ARM946EJS, but it is beyond the scope this commit. Also, filling the missing -march=* and -tune=* is left to follow-up patches. Signed-off-by: Masahiro Yamada <yamada.m@jp.panasonic.com> Acked-by: Marek Vasut <marex@denx.de> Acked-by: Stefan Roese <sr@denx.de>
* | remove unnecessary version.h includesRob Herring2015-03-24-7/+0
|/ | | | | | | | | | | | | | | | | | | | | | | | | | | | | Various files are needlessly rebuilt every time due to the version and build time changing. As version.h is not actually needed, remove the include. Signed-off-by: Rob Herring <robh@kernel.org> Cc: Albert Aribaud <albert.u.boot@aribaud.net> Cc: Stefano Babic <sbabic@denx.de> Cc: Minkyu Kang <mk7.kang@samsung.com> Cc: Marek Vasut <marex@denx.de> Cc: Tom Warren <twarren@nvidia.com> Cc: Michal Simek <monstr@monstr.eu> Cc: Macpaul Lin <macpaul@andestech.com> Cc: Wolfgang Denk <wd@denx.de> Cc: York Sun <yorksun@freescale.com> Cc: Stefan Roese <sr@denx.de> Cc: Nobuhiro Iwamatsu <iwamatsu@nigauri.org> Cc: Simon Glass <sjg@chromium.org> Cc: Philippe Reynes <tremyfr@yahoo.fr> Cc: Eric Jarrige <eric.jarrige@armadeus.org> Cc: "David Müller" <d.mueller@elsoft.ch> Cc: Phil Edworthy <phil.edworthy@renesas.com> Cc: Robert Baldyga <r.baldyga@samsung.com> Cc: Torsten Koschorrek <koschorrek@synertronixx.de> Cc: Anatolij Gustschin <agust@denx.de> Reviewed-by: Linus Walleij <linus.walleij@linaro.org> Reviewed-by: Łukasz Majewski <l.majewski@samsung.com>
* Merge branch 'master' of git://www.denx.de/git/u-boot-imxTom Rini2015-03-18-1/+18
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| * mx6: soc: Switch to cold resetDirk Behme2015-03-13-0/+18
| | | | | | | | | | | | | | | | Disable the warm reset and enable the cold reset for a more reliable restart ('reset'). This is taken from the Linux kernel, see imx_src_init() in arch/arm/mach-imx/src.c. Signed-off-by: Dirk Behme <dirk.behme@de.bosch.com>
| * imx:mx6 remove duplicated includesPeng Fan2015-03-13-1/+0
| | | | | | | | | | | | There is no need to include asm/bootm.h twice, so remove one. Signed-off-by: Peng Fan <Peng.Fan@freescale.com>
| * Merge branch 'master' of git://git.denx.de/u-bootStefano Babic2015-03-05-3648/+1523
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* | | ARM: OMAP3: rx51: Enable workaround for ARM errata 454179, 430973, 621766Nishanth Menon2015-03-13-25/+20
| | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | RX51 has a secure logic which uses different parameters compared to traditional implementation. So, make the generic secure acr write over-ride-able by board file and refactor rx51 code to use this. While at it, enable the OMAP3 specific errata code for 454179, 430973, 621766. Signed-off-by: Nishanth Menon <nm@ti.com> Reviewed-by: Tom Rini <trini@konsulko.com>
* | | ARM: OMAP3: Enable workaround for ARM errata 454179, 430973, 621766Nishanth Menon2015-03-13-21/+10
| | | | | | | | | | | | | | | | | | | | | | | | | | | Enable the OMAP3 specific errata code for 454179, 430973, 621766 and while at it, remove legacy non-revision checked errata logic. Signed-off-by: Nishanth Menon <nm@ti.com> Tested-by: Matt Porter <mporter@konsulko.com> Reviewed-by: Tom Rini <trini@konsulko.com>
* | | ARM: OMAP5 / DRA7: Setup L2 Aux Control Register with recommended configurationNishanth Menon2015-03-13-0/+16
| | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | Update to existing recommendation for L2ACTLR configuration to prevent system instability and optimize performance. These apply to both OMAP5 and DRA7. Reported-by: Vivek Chengalvala <vchengalvala@ti.com> Signed-off-by: Nishanth Menon <nm@ti.com> Reviewed-by: Tom Rini <trini@konsulko.com>
* | | ARM: DRA7 / OMAP5: Add workaround for ARM errata 798870Praveen Rao2015-03-13-0/+7
| | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | This patch enables the workaround for ARM errata 798870 for OMAP5 / DRA7 which says "If back-to-back speculative cache line fills (fill A and fill B) are issued from the L1 data cache of a CPU to the L2 cache, the second request (fill B) is then cancelled, and the second request would have detected a hazard against a recent write or eviction (write B) to the same cache line as fill B then the L2 logic might deadlock." An l2auxctlr accessor implementation for OMAP5 and DRA7 is introduced here as well. Signed-off-by: Praveen Rao <prao@ti.com> Signed-off-by: Angela Stegmaier <angelabaker@ti.com> Signed-off-by: Nishanth Menon <nm@ti.com> Tested-by: Matt Porter <mporter@konsulko.com> Reviewed-by: Tom Rini <trini@konsulko.com>
* | | ARM: OMAP3: Get rid of omap3_gp_romcode_call and replace with omap_smc1Nishanth Menon2015-03-13-16/+5
| | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | omap_smc1 is now generic enough to remove duplicate omap3_gp_romcode_call logic that omap3 introduced. As part of this change, move to using the generic lowlevel_init.S for omap3 as well. Signed-off-by: Nishanth Menon <nm@ti.com> Tested-by: Matt Porter <mporter@konsulko.com> Reviewed-by: Tom Rini <trini@konsulko.com>
* | | ARM: OMAP: Change set_pl310_ctrl_reg to be genericNishanth Menon2015-03-13-9/+13
| | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | set_pl310_ctrl_reg does use the Secure Monitor Call (SMC) to setup PL310 control register, however, that is something that is generic enough to be used for OMAP5 generation of processors as well. The only difference being the service being invoked for the function. So, convert the service to a macro and use a generic name (same as that used in Linux for some consistency). While at that, also add a data barrier which is necessary as per recommendation. While at this, smc #0 is maintained as handcoded assembly thanks to various gcc version eccentricities, discussion thread: http://marc.info/?t=142542166800001&r=1&w=2 Signed-off-by: Nishanth Menon <nm@ti.com> Tested-by: Matt Porter <mporter@konsulko.com> Reviewed-by: Tom Rini <trini@konsulko.com>
* | | ARM: Introduce erratum workaround for 621766Nishanth Menon2015-03-13-0/+13
| | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | 621766: Under a specific set of conditions, executing a sequence of NEON or vfp load instructions can cause processor deadlock Impacts: Every Cortex-A8 processors with revision lower than r2p1 Work around: Set L1NEON to 1 Based on ARM errata Document revision 20.0 (13 Nov 2010) Signed-off-by: Nishanth Menon <nm@ti.com> Tested-by: Matt Porter <mporter@konsulko.com> Reviewed-by: Tom Rini <trini@konsulko.com>
* | | ARM: Introduce erratum workaround for 430973Nishanth Menon2015-03-13-0/+13
| | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | 430973: Stale prediction on replaced inter working branch causes Cortex-A8 to execute in the wrong ARM/Thumb state Impacts: Every Cortex-A8 processors with revision lower than r2p1 Work around: Set IBE to 1 Based on ARM errata Document revision 20.0 (13 Nov 2010) Signed-off-by: Nishanth Menon <nm@ti.com> Tested-by: Matt Porter <mporter@konsulko.com> Reviewed-by: Tom Rini <trini@konsulko.com>
* | | ARM: Introduce erratum workaround for 454179Nishanth Menon2015-03-13-0/+19
| | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | 454179: Stale prediction may inhibit target address misprediction on next predicted taken branch Impacts: Every Cortex-A8 processors with revision lower than r2p1 Work around: Set IBE and disable branch size mispredict to 1 Also provide a hook for SoC specific handling to take place if needed. Based on ARM errata Document revision 20.0 (13 Nov 2010) Signed-off-by: Nishanth Menon <nm@ti.com> Tested-by: Matt Porter <mporter@konsulko.com> Reviewed-by: Tom Rini <trini@konsulko.com>
* | | ARM: Introduce erratum workaround for 798870Nishanth Menon2015-03-13-2/+48
| | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | Add workaround for Cortex-A15 ARM erratum 798870 which says "If back-to-back speculative cache line fills (fill A and fill B) are issued from the L1 data cache of a CPU to the L2 cache, the second request (fill B) is then cancelled, and the second request would have detected a hazard against a recent write or eviction (write B) to the same cache line as fill B then the L2 logic might deadlock." Implementations for SoC families such as Exynos, OMAP5/DRA7 etc will be widely different. Every SoC has slightly different manner of setting up access to L2ACLR and similar registers since the Secure Monitor handling of Secure Monitor Call(smc) is diverse. Hence an weak function is introduced which may be overriden to implement SoC specific accessor implementation. Based on ARM errata Document revision 18.0 (22 Nov 2013) Signed-off-by: Nishanth Menon <nm@ti.com> Tested-by: Matt Porter <mporter@konsulko.com> Reviewed-by: Tom Rini <trini@konsulko.com>
* | | Merge branch 'master' of git://git.denx.de/u-boot-tegraTom Rini2015-03-10-1/+8
|\ \ \ | | | | | | | | | | | | | | | | | | | | | | | | Conflicts: README Signed-off-by: Tom Rini <trini@konsulko.com>
| * | | ARM: HYP/non-sec: relocation before enable secondary coresPeng Fan2015-03-01-1/+8
| | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | If CONFIG_ARMV7_PSCI is not defined and CONFIG_ARMV7_SECURE_BASE is defined, smp_kicl_all_cpus may enable secondary cores and runs into secure_ram_addr( _smp_pen), before code is relocated to secure ram. So need relocation to secure ram before enable secondary cores. Signed-off-by: Peng Fan <Peng.Fan@freescale.com> Acked-by: Marc Zyngier <marc.zyngier@arm.com>
* | | | ARM: PSCI: Rework the DT handler slightlyTom Rini2015-03-09-1/+3
| | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | The way the PSCI DT update happens currently means we pull in <asm/armv7.h> everywhere, including on ARMv8 and that in turn brings in <asm/io.h> for some non-PSCI related things that header needs to deal with. To fix this, we rework the hook slightly. A good portion of arch/arm/cpu/armv7/virt-dt.c is common looking and I hope that when PSCI is needed on ARMv8 we can re-use this by and large. So rename the current hook to psci_update_dt(), move the prototype to <asm/psci.h> and add an #ifdef that will make re-use later easier. Reported-by: York Sun <yorksun@freescale.com> Cc: Marc Zyngier <marc.zyngier@arm.com> Cc: York Sun <yorksun@freescale.com> Cc: Ian Campbell <ijc@hellion.org.uk> Cc: Hans de Goede <hdegoede@redhat.com> Cc: Albert ARIBAUD <albert.u.boot@aribaud.net> Signed-off-by: Tom Rini <trini@konsulko.com> Acked-by: York Sun <yorksun@freescale.com>
* | | | omap: gpmc: 'nandecc sw' can use HAM1 or BCH8Ash Charles2015-03-05-1/+10
| | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | The 'nandecc sw' command selects a software-based error correction algorithm. By default, this is OMAP_ECC_HAM1_CODE_SW but some platforms use OMAP_ECC_BCH8_CODE_HW_DETECTION_SW as their software-based correction algorithm. Allow a user to be specific e.g. # nandecc sw <hamming|bch8> where 'hamming' is still the default. Note: we don't just use CONFIG_NAND_OMAP_ECCSCHEME as it might be set to a hardware-based ECC scheme---a little strange when the user has requested 'sw' ECC. Signed-off-by: Ash Charles <ashcharles@gmail.com>
* | | | omap3: add support for QUIPOS Cairo board.Albert ARIBAUD \(3ADEV\)2015-03-05-0/+5
| | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | This patch extends OMAP3 support for AM/DM37xx and introduces the AM3703-based Quipos Cairo board. Signed-off-by: Albert ARIBAUD (3ADEV) <albert.aribaud@3adev.fr> Reviewed-by: Simon Glass <sjg@chromium.org>
* | | | Merge branch 'master' of git://www.denx.de/git/u-boot-imxTom Rini2015-03-05-0/+29
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| * | Merge branch 'master' of git://git.denx.de/u-bootStefano Babic2015-03-02-4184/+808
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| * | | ARM: imx6 Add WDOG3 for i.MX6SXPeng Fan2015-02-17-0/+5
| | | | | | | | | | | | | | | | | | | | | | | | | | | | There are three wdogs for i.MX 6SoloX. Add wdog3 support in function imx_set_wdog_powerdown. Signed-off-by: Peng Fan <Peng.Fan@freescale.com>
| * | | ARM: imx6: disable bandgap self-bias after bootPeng Fan2015-02-17-0/+24
| | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | The self-bias circuit is used by the bandgap during startup. Once the bandgap has stabilized, the self-bias circuit should be disabled for best noise performance of analog blocks. Also this bit should be disabled before the chip enters STOP mode or when ever the regular bandgap is disabled. Signed-off-by: Peng Fan <Peng.Fan@freescale.com> Signed-off-by: Ranjani Vaidyanathan <Ranjani.Vaidyanathan@freescale.com>
* | | | ti: armv7: Move SPL SDRAM init to the right place, drop unused CONFIG_SPL_STACKSimon Glass2015-03-04-9/+20
| | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | Currently in some cases SDRAM init requires global_data to be available and soon this will not be available prior to board_init_f(). Adjust the code paths in these cases to be correct. In some cases we had the SPL stack be in DDR as we might have large stacks (due to Falcon Mode + Environment). In these cases switch to CONFIG_SPL_STACK_R. In other cases we had simply been setting CONFIG_SPL_STACK into SRAM. In these cases we no longer need to (CONFIG_SYS_INIT_SP_ADDR is used and is also in SRAM) so drop those lines. Signed-off-by: Simon Glass <sjg@chromium.org> Tested on Beagleboard, Beagleboard xM Tested-by: Matt Porter <mporter@konsulko.com> Tested on Beaglebone Black, AM43xx GP EVM, OMAP5 uEVM, OMAP4 Pandaboard Tested-by: Tom Rini <trini@konsulko.com> Signed-off-by: Tom Rini <trini@konsulko.com> Reviewed-by: Simon Glass <sjg@chromium.org>
* | | | arm: Reduce the scope of lowlevel_init()Simon Glass2015-03-04-2/+20
| | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | This function has grown into something of a monster. Some boards are setting up a console and DRAM here in SPL. This requires global_data which should be set up in one place (crt0.S). There is no need for SPL to use s_init() for anything since board_init_f() is called immediately afterwards. Signed-off-by: Simon Glass <sjg@chromium.org>
* | | | Merge branch 'master' of git://git.denx.de/u-boot-samsungTom Rini2015-03-01-35/+342
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| * | | | Exynos: Fix L2 cache timings on Exynos5420 and Exynos5800Doug Anderson2015-02-28-93/+77
| | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | It was found that the L2 cache timings that we had before could cause freezes and hangs. We should make things more robust with better timings. Currently the production ChromeOS kernel applies these timings, but it's nice to fixup firmware too (and upstream probably won't take our kernel hacks). This also provides a big cleanup of the L2 cache init code avoiding some duplication. The way things used to work: * low_power_start() was installed by the SPL (both at boot and resume time) and left resident in iRAM for the kernel to use when bringing up additional CPUs. It used configure_l2_ctlr() and configure_l2_actlr() when it detected it was on an A15. This was needed (despite the L2 cache registers being shared among all A15s) because we might have been the first man in after the whole A15 cluster was shutdown. * secondary_cores_configure() was called on at boot time and at resume time. Strangely this called configure_l2_ctlr() but not configure_l2_actlr() which was almost certainly wrong. Given that we'll call both (see next bullet) later in the boot process it didn't matter for normal boot, but I guess this is how L2 cache settings got set on 5420/5800 (but not 5250?) at resume time. * exynos5_set_l2cache_params() was called as part of cache enablement. This should happen at boot time (normally in the SPL except for USB boot where it happens in main U-Boot). Note that the old code wasn't setting ECC/parity in the cache enablement code but we happened to get it anyway because we'd call secondary_cores_configure() at boot time. For resume time we'd get it anyway when the 2nd A15 core came up. Let's make this a whole lot simpler. Now we always set these parameters in the same place for all boots and use the same code for setting up secondary CPUs. Intended net effects of this change (other than cleanup): * Timings go from before: data: 0 cycle setup, 3 cycles (0x2) latency tag: 0 cycle setup, 3 cycles (0x2) latency after: data: 1 cycle setup, 4 cycles (0x3) latency tag: 1 cycle setup, 4 cycles (0x3) latency * L2ACTLR is properly initted on 5420/5800 in all cases. One note is that we're still relying on luck to keep low_power_start() working. The compiler is being nice and not storing anything on the stack. Another note is that on its own this patch won't help to fix cache settings in an RW U-Boot update where we still have the RO SPL. The plan for that is: * Have RW U-Boot re-init the cache right before calling the kernel (after it has turned the L2 cache off). This is why the functions are in a header file instead of lowlevel_init.c. * Have the kernel save the L2 cache settings of the boot CPU and apply them to all other CPUs. We get a little lucky here because the old code was using "|=" to modify the registers and all of the bits that it's setting are also present in the new settings (!). That means that when the 2nd CPU in the A15 cluster comes up it doesn't actually mess up the settings of the 1st CPU in the A15 cluster. An alternative option is to have the kernel write its own low_power_start() code. Signed-off-by: Doug Anderson <dianders@chromium.org> Signed-off-by: Akshay Saraswat <akshay.s@samsung.com> Signed-off-by: Minkyu Kang <mk7.kang@samsung.com>
| * | | | Exynos542x: Make A7s boot with thumb-mode U-Boot on warm resetAkshay Saraswat2015-02-28-1/+1
| | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | On warm reset, all cores jump to the low_power_start function because iRAM data is retained and because while executing iROM code all cores find the jump flag 0x02020028 set. In low_power_start, cores check the reset status and if true they clear the jump flag and jump back to 0x0. The A7 cores do jump to 0x0 but consider following instructions as a Thumb instructions which in turn makes them loop inside the iROM code instead of jumping to power_down_core. This issue is fixed by replacing the "mov pc" instruction with a "bx" instruction which switches state along with the jump to make the execution unit consider the branch target as an ARM instruction. Signed-off-by: Akshay Saraswat <akshay.s@samsung.com> Reviewed-by: Simon Glass <sjg@chromium.org> Tested-by: Simon Glass <sjg@chromium.org> Signed-off-by: Minkyu Kang <mk7.kang@samsung.com>
| * | | | Exynos542x: Fix secondary core booting for thumbAkshay Saraswat2015-02-28-1/+1
| | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | When compiled SPL for Thumb secondary cores failed to boot at the kernel boot up. Only one core came up out of 4. This was happening because the code relocated to the address 0x02073000 by the primary core was an ARM asm code which was executed by the secondary cores as if it was a thumb code. This patch fixes the issue of secondary cores considering relocated code as Thumb instructions and not ARM instructions by jumping to the relocated with the help of "bx" ARM instruction. "bx" instruction changes the 5th bit of CPSR which allows execution unit to consider the following instructions as ARM instructions. Signed-off-by: Akshay Saraswat <akshay.s@samsung.com> Reviewed-by: Simon Glass <sjg@chromium.org> Tested-by: Simon Glass <sjg@chromium.org> Signed-off-by: Minkyu Kang <mk7.kang@samsung.com>
generated by cgit v1.1 at 2024-11-05 22:52:32 +0000