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| author | Nishanth Menon <nm@ti.com> | 2015-03-09 17:12:07 -0500 |
|---|---|---|
| committer | Tom Rini <trini@konsulko.com> | 2015-03-13 09:29:13 -0400 |
| commit | fc7368ec858fc735866e7928a326a8e2a84c5696 (patch) | |
| tree | 4b39051b117150235c2860c734f28c5c39cb2ab3 /arch/arm/cpu/armv7 | |
| parent | 5f603761c3de00423cad405e064cd2fc822feab1 (diff) | |
| download | u-boot-imx-fc7368ec858fc735866e7928a326a8e2a84c5696.zip u-boot-imx-fc7368ec858fc735866e7928a326a8e2a84c5696.tar.gz u-boot-imx-fc7368ec858fc735866e7928a326a8e2a84c5696.tar.bz2 | |
ARM: OMAP5 / DRA7: Setup L2 Aux Control Register with recommended configuration
Update to existing recommendation for L2ACTLR configuration to prevent
system instability and optimize performance.
These apply to both OMAP5 and DRA7.
Reported-by: Vivek Chengalvala <vchengalvala@ti.com>
Signed-off-by: Nishanth Menon <nm@ti.com>
Reviewed-by: Tom Rini <trini@konsulko.com>
Diffstat (limited to 'arch/arm/cpu/armv7')
| -rw-r--r-- | arch/arm/cpu/armv7/omap5/hwinit.c | 16 |
1 files changed, 16 insertions, 0 deletions
diff --git a/arch/arm/cpu/armv7/omap5/hwinit.c b/arch/arm/cpu/armv7/omap5/hwinit.c index f806055..8d6b59e 100644 --- a/arch/arm/cpu/armv7/omap5/hwinit.c +++ b/arch/arm/cpu/armv7/omap5/hwinit.c @@ -304,6 +304,21 @@ void config_data_eye_leveling_samples(u32 emif_base) (*ctrl)->control_emif2_sdram_config_ext); } +void init_cpu_configuration(void) +{ + u32 l2actlr; + + asm volatile("mrc p15, 1, %0, c15, c0, 0" : "=r"(l2actlr)); + /* + * L2ACTLR: Ensure to enable the following: + * 3: Disable clean/evict push to external + * 4: Disable WriteUnique and WriteLineUnique transactions from master + * 8: Disable DVM/CMO message broadcast + */ + l2actlr |= 0x118; + omap_smc1(OMAP5_SERVICE_L2ACTLR_SET, l2actlr); +} + void init_omap_revision(void) { /* @@ -342,6 +357,7 @@ void init_omap_revision(void) default: *omap_si_rev = OMAP5430_SILICON_ID_INVALID; } + init_cpu_configuration(); } void reset_cpu(ulong ignored) |