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* ARM: zynq: Do not use half memory size for ECC caseMichal Simek2014-05-14-3/+0
| | | | | | | | Memory size should be specified without ECC place. If you need to have half memory size, please change u-boot configuration. Signed-off-by: Michal Simek <michal.simek@xilinx.com>
* ARM: zynq: Added efuse status register base addressSiva Durga Prasad Paladugu2014-05-14-0/+13
| | | | | | | | | | Added efuse status register base address. This register is used for determining whether efuse was blown or not. Also, added the zynq_get_silicon_version() to get the silicon version of the zynq board. Signed-off-by: Siva Durga Prasad Paladugu <sivadur@xilinx.com> Signed-off-by: Michal Simek <michal.simek@xilinx.com>
* ARM: zynq: Fix sparse warning in ddrc.cMichal Simek2014-05-14-1/+1
| | | | | | | Warning: arch/arm/cpu/armv7/zynq/ddrc.c:43:24: warning: Using plain integer as NULL pointer Signed-off-by: Michal Simek <michal.simek@xilinx.com>
* ARM: zynq: Fix sparse warnings in slcr.cMichal Simek2014-05-14-0/+1
| | | | | | | | | | | | | | Warnings: arch/arm/cpu/armv7/zynq/slcr.c:21:6: warning: symbol 'zynq_slcr_lock' was not declared. Should it be static? arch/arm/cpu/armv7/zynq/slcr.c:27:6: warning: symbol 'zynq_slcr_unlock' was not declared. Should it be static? arch/arm/cpu/armv7/zynq/slcr.c:34:6: warning: symbol 'zynq_slcr_cpu_reset' was not declared. Should it be static? arch/arm/cpu/armv7/zynq/slcr.c:54:6: warning: symbol 'zynq_slcr_gem_clk_setup' was not declared. Should it be static? arch/arm/cpu/armv7/zynq/slcr.c:81:6: warning: symbol 'zynq_slcr_devcfg_disable' was not declared. Should it be static? arch/arm/cpu/armv7/zynq/slcr.c:94:6: warning: symbol 'zynq_slcr_devcfg_enable' was not declared. Should it be static? arch/arm/cpu/armv7/zynq/slcr.c:107:5: warning: symbol 'zynq_slcr_get_boot_mode' was not declared. Should it be static? arch/arm/cpu/armv7/zynq/slcr.c:113:5: warning: symbol 'zynq_slcr_get_idcode' was not declared. Should it be static? Signed-off-by: Michal Simek <michal.simek@xilinx.com>
* arm: make _end compiler-generatedAlbert ARIBAUD2014-02-26-1/+6
| | | | | | | | | This prevents references to _end from generating absolute relocation records. This change is binary invariant for ARM targets. Signed-off-by: Albert ARIBAUD <albert.u.boot@aribaud.net>
* arm: zynq: correct the argument to lldivSiva Durga Prasad Paladugu2014-02-19-1/+2
| | | | | | | | Typecast the argument with unsigned long long for proper calculation of lldiv Signed-off-by: Siva Durga Prasad Paladugu <sivadur@xilinx.com> Signed-off-by: Michal Simek <michal.simek@xilinx.com>
* zynq: Add support for U-BOOT SPLMichal Simek2014-02-19-2/+133
| | | | | | | | | | | | | | | | | SPL is using ps7_init.c/h files which are generated from design tools which have to be copied to boards/xilinx/zynq folder before compilation. BSS section is moved to SDRAM because fat support requires more space than SRAM size. Added: - MMC and QSPI support - Boot OS directly from SPL - Enable SPL command Signed-off-by: Michal Simek <michal.simek@xilinx.com> Reviewed-by: Tom Rini <trini@ti.com>
* zynq: Update CLK in bdinfoMichal Simek2014-02-19-0/+5
| | | | | | ARM has specific clk entries which should be also setup. Signed-off-by: Michal Simek <michal.simek@xilinx.com>
* zynq: Implement dump clock commandSoren Brinkmann2014-02-19-0/+21
| | | | | | | | Enable and implement dump clock command which shows soc frequencies. Signed-off-by: Soren Brinkmann <soren.brinkmann@xilinx.com> Signed-off-by: Michal Simek <michal.simek@xilinx.com>
* net: zynq_gem: Calculate clock dividers dynamicallySoren Brinkmann2014-02-19-5/+8
| | | | | | | | Remove hard coded clock divider setting and use the Zynq clock framework to dynamically calculate appropriate dividers at run time. Signed-off-by: Soren Brinkmann <soren.brinkmann@xilinx.com> Signed-off-by: Michal Simek <michal.simek@xilinx.com>
* net: zynq_gem: Move RCLK details out of driverSoren Brinkmann2014-02-19-3/+3
| | | | | | | | | The GEM driver should not need to know about Zynq specific details of RCLK related registers and bitfields in the SLCR. Move those details to the slcr driver. Signed-off-by: Soren Brinkmann <soren.brinkmann@xilinx.com> Signed-off-by: Michal Simek <michal.simek@xilinx.com>
* zynq: timer: Fix hangs if network activity attempted after about one hourMichal Simek2014-02-19-2/+2
| | | | | | | | | | | | Cortex-A9 MPCore TRM' from ARM (ARM DDI 0407G ID072711) describes in the section 4.1.1 how this value calculation should be done. This patch fixes the problem if network activity such as ping or tftp is attempted after u-boot has been idle for an hour, it hangs, and cannot control-C out of it. Signed-off-by: Uday Hegde <udayh@xilinx.com> Signed-off-by: Michal Simek <michal.simek@xilinx.com>
* zynq: timer: Migrate to zynq clock frameworkSoren Brinkmann2014-02-19-4/+7
| | | | | | | Remove hardcoded frequencies in favor of Zynq clock framework. Signed-off-by: Soren Brinkmann <soren.brinkmann@xilinx.com> Signed-off-by: Michal Simek <michal.simek@xilinx.com>
* zynq: Provide a framework to read clock frequenciesSoren Brinkmann2014-02-19-0/+641
| | | | | Signed-off-by: Soren Brinkmann <soren.brinkmann@xilinx.com> Signed-off-by: Michal Simek <michal.simek@xilinx.com>
* zynq: Enable dcache supportMichal Simek2014-02-19-0/+8
| | | | | | Enable dcache. Signed-off-by: Michal Simek <michal.simek@xilinx.com>
* zynq: Fix elf header generationMichal Simek2014-02-13-0/+99
| | | | | | | | | | | | This patch is here because of: "arm: keep all sections in ELF file" (sha1: 47ed5dd031d7d2c587e6afd386e79ccec1a1b7f7) Our tools expect to have elf with only LOAD header. Without this fix also PHDR, INTERP and DYNAMIC headers are available in ELF. Signed-off-by: Michal Simek <michal.simek@xilinx.com>
* Merge branch 'master' of git://git.denx.de/u-boot-armTom Rini2014-01-10-0/+6
|\ | | | | | | | | | | | | | | | | | | Bringing in the MMC tree means that CONFIG_BOUNCE_BUFFER needed to be added to include/configs/exynos5-dt.h now. Conflicts: include/configs/exynos5250-dt.h Signed-off-by: Tom Rini <trini@ti.com>
| * zynq: Add support to find bootmodeJagannadha Sutradharudu Teki2014-01-10-0/+6
| | | | | | | | | | | | | | | | | | | | | | Added support to find the bootmodes by reading slcr bootmode register. this can be helpful to autoboot the configurations w.r.t a specified bootmode. Added this functionality on board_late_init as it's not needed for normal initializtion part. Signed-off-by: Jagannadha Sutradharudu Teki <jaganna@xilinx.com>
* | ARM:zynq: Correct __udelay to use lldivTom Rini2013-12-13-2/+1
|/ | | | | Cc: Michal Simek <monstr@monstr.eu> Signed-off-by: Tom Rini <trini@ti.com>
* Merge branch 'u-boot-microblaze/zynq' into 'u-boot-arm/master'Albert ARIBAUD2013-11-22-4/+5
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| * arm: zynq : Revert TZ_DDR_RAM to secure.Radhey Shyam Pandey2013-11-06-2/+0
| | | | | | | | | | | | | | | | | | | | TZ_DDR_RAM on reset is in secure mode. Since uboot and linux runs in full TZ privilege secure mode, no need to set DDR trustzone to non-secure. Signed-off-by: Radhey Shyam Pandey <radheys@xilinx.com> Signed-off-by: Michal Simek <michal.simek@xilinx.com>
| * arm: zynq: Do not remap OCM to high addressMichal Simek2013-11-06-2/+5
| | | | | | | | | | | | | | | | In case where ps-ddr is not used, do not remap OCM to high address and keep it from 0x0. Linux SMP requires to have memory at 0x0. Signed-off-by: Michal Simek <michal.simek@xilinx.com>
* | Merge branch 'iu-boot/master' into 'u-boot-arm/master'Albert ARIBAUD2013-11-09-0/+6
|\ \ | |/ | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | Conflicts: arch/arm/cpu/arm926ejs/mxs/Makefile board/compulab/cm_t35/Makefile board/corscience/tricorder/Makefile board/ppcag/bg0900/Makefile drivers/bootcount/Makefile include/configs/omap4_common.h include/configs/pdnb3.h Makefile conflicts are due to additions/removals of object files on the ARM branch vs KBuild introduction on the main branch. Resolution consists in adjusting the list of object files in the main branch version. This also applies to two files which are not listed as conflicting but had to be modified: board/compulab/common/Makefile board/udoo/Makefile include/configs/omap4_common.h conflicts are due to the OMAP4 conversion to ti_armv7_common.h on the ARM side, and CONFIG_SYS_HZ removal on the main side. Resolution is to convert as this icludes removal of CONFIG_SYS_HZ. include/configs/pdnb3.h is due to a removal on ARM side. Trivial resolution is to remove the file. Note: 'git show' will also list two files just because they are new: include/configs/am335x_igep0033.h include/configs/omap3_igep00x0.h
| * zynq: Use arch_cpu_init() instead of lowlevel_init()Michal Simek2013-10-17-0/+6
| | | | | | | | | | | | | | | | | | | | | | Zynq lowlevel_init() was implemented in C but stack pointer is setup after function call in _main(). Move architecture setup to arch_cpu_init() which is call as the first function in board_init_f() which already have correct stack pointer. Reported-by: Sven Schwermer <sven.schwermer@tuhh.de> Signed-off-by: Michal Simek <michal.simek@xilinx.com>
* | armv7: convert makefiles to Kbuild styleMasahiro Yamada2013-10-31-27/+4
|/ | | | Signed-off-by: Masahiro Yamada <yamada.m@jp.panasonic.com>
* Coding Style cleanup: remove trailing white spaceWolfgang Denk2013-10-14-2/+2
| | | | Signed-off-by: Wolfgang Denk <wd@denx.de>
* arm: zynq: Fix timer loadaddressMichal Simek2013-09-23-1/+1
| | | | | | | | | | Reload address was written to the counter register instead of load register. The problem happens when timer expires but never reload to ~0UL (it is downcount timer). Reported-by: Stephen MacMahon <stephenm@xilinx.com> Signed-off-by: Michal Simek <michal.simek@xilinx.com>
* zynq: slcr: Wait 100ms till clk is properly setupMichal Simek2013-08-12-1/+1
| | | | | | | | If you don't wait you will loose the first sent packet even all bits in emacps are correctly setup. Signed-off-by: Michal Simek <michal.simek@xilinx.com> Acked-by: Jagannadha Sutradharudu Teki <jaganna@xilinx.com>
* zynq: Add new ddrc driver for ECC supportMichal Simek2013-08-12-0/+51
| | | | | | | | | | The first 1MB is not initialized by first stage bootloader. Check if memory is setup to 16bit mode and ECC is enabled. If it is, clear the first 1MB. Also u-boot should report only the half size of memory. Acked-by: Jagannadha Sutradharudu Teki <jaganna@xilinx.com> Signed-off-by: Michal Simek <michal.simek@xilinx.com>
* Add GPL-2.0+ SPDX-License-Identifier to source filesWolfgang Denk2013-07-24-68/+4
| | | | | | Signed-off-by: Wolfgang Denk <wd@denx.de> [trini: Fixup common/cmd_io.c] Signed-off-by: Tom Rini <trini@ti.com>
* fpga: zynq: Add support for loading bitstreamMichal Simek2013-05-06-0/+35
| | | | | | | | | | | | | Devcfg device requires to load bitstream in binary format. But u-boot also has an option for loading bitstream in bit format. Let's handle both cases by zynqpl driver. Also add suport for loading partial bitstreams. The first driver version was done by: Joe Hershberger <joe.hershberger@ni.com> Signed-off-by: Michal Simek <michal.simek@xilinx.com> Reviewed-by: Tom Rini <trini@ti.com>
* net: gem: Fix gem driver on 1Gbps LANMichal Simek2013-04-30-0/+26
| | | | | | | | | | The whole driver used 100Mbps because of zc702 rev B. Fix problem with not setup proper clock for gem1. This is generic approach for clk setup. Signed-off-by: Michal Simek <monstr@monstr.eu> Signed-off-by: Michal Simek <michal.simek@xilinx.com> Reviewed-by: Tom Rini <trini@ti.com>
* zynq: Move scutimer baseaddr to hardware.hMichal Simek2013-04-30-1/+2
| | | | | | | | Move baseaddr to hardware.h to be shared between configurations. Signed-off-by: Michal Simek <michal.simek@xilinx.com> Reviewed-by: Tom Rini <trini@ti.com>
* arm: zynq: U-Boot udelay < 1000 FIXDavid Andrey2013-04-30-9/+37
| | | | | | | | | Rework the __udelay function of U-Boot Zynq Arch to handle delay < 1000 usec Signed-off-by: David Andrey <david.andrey@netmodule.com> Signed-off-by: Michal Simek <michal.simek@xilinx.com> Reviewed-by: Tom Rini <trini@ti.com>
* arm: zynq: Add lowlevel initialization to CMichal Simek2013-02-07-1/+25
| | | | | | | Do lowlevel initialization directly in C. Zynq do not require to do it in asm. Signed-off-by: Michal Simek <michal.simek@xilinx.com>
* arm: zynq: Add SLCR support with system resetMichal Simek2013-02-07-0/+66
| | | | | | | | | The patch provides slcr base address initialization support and a support to reset the cpu through slcr driver, hence removed the reset_cpu() from board.c. Signed-off-by: Jagannadha Sutradharudu Teki <jaganna@xilinx.com> Signed-off-by: Michal Simek <michal.simek@xilinx.com>
* arm: Move lastinc to arch_global_dataSimon Glass2013-02-01-5/+5
| | | | | | Move this field into arch_global_data and tidy up. Signed-off-by: Simon Glass <sjg@chromium.org>
* arm: Move tbl to arch_global_dataSimon Glass2013-02-01-4/+4
| | | | | | Move this field into arch_global_data and tidy up. Signed-off-by: Simon Glass <sjg@chromium.org>
* arm: Support new Xilinx Zynq platformMichal Simek2012-10-04-0/+232
Add timer driver. Signed-off-by: Michal Simek <monstr@monstr.eu> CC: Joe Hershberger <joe.hershberger@gmail.com> CC: Marek Vasut <marex@denx.de> Acked-by: Marek Vasut <marex@denx.de>
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