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authorMichal Simek <monstr@monstr.eu>2012-10-15 14:01:23 +0200
committerMichal Simek <michal.simek@xilinx.com>2013-04-30 11:39:19 +0200
commit80243528efa5e17db60328005344bb8a5e8e8076 (patch)
tree8dbcc857b681a640ebd90eb7ec8f11daa003668c /arch/arm/cpu/armv7/zynq
parent058687597d3ff26c415db33614b881de258a365b (diff)
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net: gem: Fix gem driver on 1Gbps LAN
The whole driver used 100Mbps because of zc702 rev B. Fix problem with not setup proper clock for gem1. This is generic approach for clk setup. Signed-off-by: Michal Simek <monstr@monstr.eu> Signed-off-by: Michal Simek <michal.simek@xilinx.com> Reviewed-by: Tom Rini <trini@ti.com>
Diffstat (limited to 'arch/arm/cpu/armv7/zynq')
-rw-r--r--arch/arm/cpu/armv7/zynq/slcr.c26
1 files changed, 26 insertions, 0 deletions
diff --git a/arch/arm/cpu/armv7/zynq/slcr.c b/arch/arm/cpu/armv7/zynq/slcr.c
index 788a8fd..5a8674a 100644
--- a/arch/arm/cpu/armv7/zynq/slcr.c
+++ b/arch/arm/cpu/armv7/zynq/slcr.c
@@ -61,3 +61,29 @@ void zynq_slcr_cpu_reset(void)
writel(1, &slcr_base->pss_rst_ctrl);
}
+
+/* Setup clk for network */
+void zynq_slcr_gem_clk_setup(u32 gem_id, u32 rclk, u32 clk)
+{
+ zynq_slcr_unlock();
+
+ if (gem_id > 1) {
+ printf("Non existing GEM id %d\n", gem_id);
+ goto out;
+ }
+
+ if (gem_id) {
+ /* Set divisors for appropriate frequency in GEM_CLK_CTRL */
+ writel(clk, &slcr_base->gem1_clk_ctrl);
+ /* Configure GEM_RCLK_CTRL */
+ writel(rclk, &slcr_base->gem1_rclk_ctrl);
+ } else {
+ /* Set divisors for appropriate frequency in GEM_CLK_CTRL */
+ writel(clk, &slcr_base->gem0_clk_ctrl);
+ /* Configure GEM_RCLK_CTRL */
+ writel(rclk, &slcr_base->gem0_rclk_ctrl);
+ }
+
+out:
+ zynq_slcr_lock();
+}