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* | Merge branch 'rmobile' of git://git.denx.de/u-boot-shTom Rini2015-03-01-41/+3349
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| * | arm: rmobile: silk: Add support SDHIVladimir Barinov2015-02-25-1/+38
| | | | | | | | | | | | | | | | | | | | | This adds GPIO configuration and initialization function of SDHI on Silk board Signed-off-by: Vladimir Barinov <vladimir.barinov+renesas@cogentembedded.com> Signed-off-by: Nobuhiro Iwamatsu <iwamatsu@nigauri.org>
| * | arm: rmobile: silk: fix typo in device declarationVladimir Barinov2015-02-25-1/+1
| | | | | | | | | | | | | | | | | | | | | Fix typo in device declaration Signed-off-by: Vladimir Barinov <vladimir.barinov+renesas@cogentembedded.com> Signed-off-by: Nobuhiro Iwamatsu <iwamatsu@nigauri.org>
| * | arm: rmobile: silk: Disable ethernet pins pull-upVladimir Barinov2015-02-25-0/+8
| | | | | | | | | | | | | | | | | | | | | Disable pull-ups on ethrenet lines Signed-off-by: Vladimir Barinov <vladimir.barinov+renesas@cogentembedded.com> Signed-off-by: Nobuhiro Iwamatsu <iwamatsu@nigauri.org>
| * | arm: rmobile: silk: Fix GPIO4_31 initializationVladimir Barinov2015-02-25-1/+1
| | | | | | | | | | | | | | | | | | | | | | | | | | | Use gpio_direction_output instead of gpio_set_value since the latter does not set output GPIO direction. Signed-off-by: Valentine Barshak <valentine.barshak+renesas@cogentembedded.com> Signed-off-by: Vladimir Barinov <vladimir.barinov+renesas@cogentembedded.com> Signed-off-by: Nobuhiro Iwamatsu <iwamatsu@nigauri.org>
| * | arm: rmobile: Add Porter board supportVladimir Barinov2015-02-25-1/+1704
| | | | | | | | | | | | | | | | | | | | | | | | | | | | | | Porter is an entry level development board based on R-Car M2 SoC (R8A7791) This commit supports the following peripherals: - SCIF, I2C, Ethernet, QSPI, SD, USB Host Signed-off-by: Vladimir Barinov <vladimir.barinov@cogentembedded.com> Signed-off-by: Nobuhiro Iwamatsu <iwamatsu@nigauri.org>
| * | arm: rmobile: lager: Add support SDHINobuhiro Iwamatsu2015-02-25-9/+1055
| | | | | | | | | | | | | | | | | | | | | | | | | | | Lager board has two SDHI port as SDHI0 and SDHI2. This adds GPIO configuration and initialization function of SDHI, and enables MMC command. Signed-off-by: Nobuhiro Iwamatsu <nobuhiro.iwamatsu.yj@renesas.com> Signed-off-by: Nobuhiro Iwamatsu <iwamatsu@nigauri.org>
| * | arm: rmobile: gose: Add support SDHINobuhiro Iwamatsu2015-02-25-0/+74
| | | | | | | | | | | | | | | | | | | | | | | | | | | Gose board has three SDHI port. This adds GPIO configuration and initialization function of SDHI, and enables MMC command. Signed-off-by: Nobuhiro Iwamatsu <nobuhiro.iwamatsu.yj@renesas.com> Signed-off-by: Nobuhiro Iwamatsu <iwamatsu@nigauri.org>
| * | arm: rmobile: koelsch: Add support SDHINobuhiro Iwamatsu2015-02-25-1/+79
| | | | | | | | | | | | | | | | | | | | | | | | | | | Koelsch board has three SDHI port. This adds GPIO configuration and initialization function of SDHI, and enables MMC command. Signed-off-by: Nobuhiro Iwamatsu <nobuhiro.iwamatsu.yj@renesas.com> Signed-off-by: Nobuhiro Iwamatsu <iwamatsu@nigauri.org>
| * | arm: rmobile: alt: Add support SDHINobuhiro Iwamatsu2015-02-25-13/+308
| | | | | | | | | | | | | | | | | | | | | | | | | | | Alt board has two SDHI port. This adds GPIO configuration and initialization function of SDHI, and enables MMC command. Signed-off-by: Nobuhiro Iwamatsu <nobuhiro.iwamatsu.yj@renesas.com> Signed-off-by: Nobuhiro Iwamatsu <iwamatsu@nigauri.org>
| * | arm: rmobile: silk: Migrate serial driver to drivers modelNobuhiro Iwamatsu2015-02-25-3/+16
| | | | | | | | | | | | | | | | | | | | | | | | This adds drivers model support of serial port to Silk board, and migrate serial port to drivers model. Signed-off-by: Nobuhiro Iwamatsu <nobuhiro.iwamatsu.yj@renesas.com> Signed-off-by: Nobuhiro Iwamatsu <iwamatsu@nigauri.org>
| * | arm: rmobile: alt: Migrate serial driver to drivers modelNobuhiro Iwamatsu2015-02-25-3/+16
| | | | | | | | | | | | | | | | | | | | | | | | This adds drivers model support of serial port to Alt board, and migrate serial port to drivers model. Signed-off-by: Nobuhiro Iwamatsu <nobuhiro.iwamatsu.yj@renesas.com> Signed-off-by: Nobuhiro Iwamatsu <iwamatsu@nigauri.org>
| * | arm: rmobile: lager: Migrate serial driver to drivers modelNobuhiro Iwamatsu2015-02-25-3/+16
| | | | | | | | | | | | | | | | | | | | | | | | This adds drivers model support of serial port to Lager board, and migrate serial port to drivers model. Signed-off-by: Nobuhiro Iwamatsu <nobuhiro.iwamatsu.yj@renesas.com> Signed-off-by: Nobuhiro Iwamatsu <iwamatsu@nigauri.org>
| * | arm: rmobile: gose: Migrate serial driver to drivers modelNobuhiro Iwamatsu2015-02-25-3/+16
| | | | | | | | | | | | | | | | | | | | | | | | This adds drivers model support of serial port to Gose board, and migrate serial port to drivers model. Signed-off-by: Nobuhiro Iwamatsu <nobuhiro.iwamatsu.yj@renesas.com> Signed-off-by: Nobuhiro Iwamatsu <iwamatsu@nigauri.org>
| * | arm: rmobile: koelsch: Migrate serial driver to drivers modelNobuhiro Iwamatsu2015-02-25-3/+18
| | | | | | | | | | | | | | | | | | | | | | | | This adds drivers model support of serial port to Koelsch board, and migrate serial port to drivers model. Signed-off-by: Nobuhiro Iwamatsu <nobuhiro.iwamatsu.yj@renesas.com> Signed-off-by: Nobuhiro Iwamatsu <iwamatsu@nigauri.org>
* | | Merge branch 'master' of git://git.denx.de/u-boot-shTom Rini2015-03-01-5/+943
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| * | | sh: enable CONFIG_USE_PRIVATE_LIBGCC by defaultMasahiro Yamada2015-02-25-0/+3
| | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | Now this feature works. Let's turn it on by default so we do not depend on specific tool-chains. Signed-off-by: Masahiro Yamada <yamada.m@jp.panasonic.com> Signed-off-by: Nobuhiro Iwamatsu <iwamatsu@nigauri.org>
| * | | sh: import missing private libraries from Linux 3.19Masahiro Yamada2015-02-25-2/+936
| | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | SuperH is supposed to support the Private Library feature, but it is actually not working. If CONFIG_USE_PRIVATE_LIBGCC is enabled, the build fails for the undefined references to '__sdivsi3_i4i' and '__udivsi3_i4i'. To fix this error, import missing libraries from Linux 3.19 and adjust them for U-Boot: - Remove "#include <linux/module.h>" and "EXPORT_SYMBOL(...)" - Use SPDX-License-Identifier - Remove white space Signed-off-by: Masahiro Yamada <yamada.m@jp.panasonic.com> Signed-off-by: Nobuhiro Iwamatsu <iwamatsu@nigauri.org>
| * | | sh: rename some private librariesMasahiro Yamada2015-02-25-2/+2
| | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | Rename two files to the corresponding file names in Linux. This helps us find missing libraries in the next commit. Signed-off-by: Masahiro Yamada <yamada.m@jp.panasonic.com> Signed-off-by: Nobuhiro Iwamatsu <iwamatsu@nigauri.org>
| * | | serial: sh: fix internal clock source on SCIFVladimir Barinov2015-02-25-2/+3
| | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | The formula to calculate SCIF BRR for R-Car H2/M2/E2 SoCs is as follows: BRR = pclk / (64 * 2^(2n-1) * baudrate) - 1, the prescaler is 0 due to SCSMR settings, hence n=0 Also SCSCR must be set to use internal or external clock source. Signed-off-by: Vladimir Barinov <vladimir.barinov@cogentembedded.com> Signed-off-by: Nobuhiro Iwamatsu <iwamatsu@nigauri.org>
| * | | serial: sh: Remove invalid UTF-8 characterNobuhiro Iwamatsu2015-02-25-1/+1
| |/ / | | | | | | | | | | | | | | | | | | | | | serial_sh.c contains invalid UTF-8 character. This deletes the character. Signed-off-by: Nobuhiro Iwamatsu <nobuhiro.iwamatsu.yj@renesas.com> Signed-off-by: Nobuhiro Iwamatsu <iwamatsu@nigauri.org>
* | | MAINTAINERS: Add F: drivers/usb/gadget to DFU custodian responsibilityLukasz Majewski2015-02-26-0/+1
| |/ |/| | | | | | | | | | | | | | | | | After discussion during the last u-boot mini summit with USB maintainer - Marek Vasut - it has been decided, that gadget development should be coordinated by DFU custodian. Such patch formalizes current development status. Signed-off-by: Lukasz Majewski <l.majewski@samsung.com>
* | Merge branch 'master' of git://git.denx.de/u-boot-fsl-qoriqTom Rini2015-02-25-334/+2404
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| * | crypto/fsl - Add progressive hashing support using hardware acceleration.gaurav rana2015-02-25-7/+302
| | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | Currently only normal hashing is supported using hardware acceleration. Added support for progressive hashing using hardware. Signed-off-by: Ruchika Gupta <ruchika.gupta@freescale.com> Signed-off-by: Gaurav Rana <gaurav.rana@freescale.com> CC: Simon Glass <sjg@chromium.org> Reviewed-by: Simon Glass <sjg@chromium.org> Reviewed-by: York Sun <yorksun@freescale.com>
| * | crypto/fsl: Make function names consistent for blob encapsulation/decapsulation.gaurav rana2015-02-25-10/+12
| | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | This patch does the following: 1. The function names for encapsulation and decapsulation were inconsitent in freescale's implementation and cmd_blob file. This patch corrects the issues. 2. The function protopye is also modified to change the length parameter from u8 to u32 to allow encapsulation and decapsulation of larger images. 3. Modified the description of km paramter in the command usage for better readability. Signed-off-by: Gaurav Rana <gaurav.rana@freescale.com> Reviewed-by: Ruchika Gupta <ruchika.gupta@freescale.com> Reviewed-by: York Sun <yorksun@freescale.com>
| * | mmc: fsl_esdhc: Add support for DDR modeVolodymyr Riazantsev2015-02-24-2/+9
| | | | | | | | | | | | | | | | | | | | | | | | Add support of the DDR mode for eSDHC driver. Enable it for i.MX6 SoC family only. Signed-off-by: Volodymyr Riazantsev <volodymyr.riazantsev@globallogic.com> Reviewed-by: York Sun <yorksun@freescale.com>
| * | arm: ls1021x: Add support for initializing CAAM's stream idAlison Wang2015-02-24-0/+115
| | | | | | | | | | | | | | | | | | | | | | | | | | | There 4 JRs, 4 RTICs and 8 DECOs, and set them the same stream id for using the same SMMU3 on LS1021A. Signed-off-by: Xiubo Li <Li.Xiubo@freescale.com> Signed-off-by: Alison Wang <alison.wang@freescale.com> Reviewed-by: York Sun <yorksun@freescale.com>
| * | arm: ls102xa: workaround for cache coherency problemchenhui zhao2015-02-24-0/+28
| | | | | | | | | | | | | | | | | | | | | | | | | | | | | | The RCPM FSM may not be reset after power-on, for example, in the cases of cold boot and wakeup from deep sleep. It causes cache coherency problem and may block deep sleep. Therefore, reset them if they are not be reset. Signed-off-by: Chenhui Zhao <chenhui.zhao@freescale.com> Reviewed-by: York Sun <yorksun@freescale.com>
| * | driver/pci: add Layerscape PCIe driverMinghuan Lian2015-02-24-5/+466
| | | | | | | | | | | | | | | | | | | | | | | | The patch adds Freescale Layerscape PCIe driver and provides up to 4 controllers support. Signed-off-by: Minghuan Lian <Minghuan.Lian@freescale.com> Reviewed-by: York Sun <yorksun@freescale.com>
| * | arm/ls1021a: add PCIe settingsMinghuan Lian2015-02-24-0/+48
| | | | | | | | | | | | | | | | | | | | | | | | The patch enables and adds PCIe settings for boards LS1021AQDS and LS1021ATWR. Signed-off-by: Minghuan Lian <Minghuan.Lian@freescale.com> Reviewed-by: York Sun <yorksun@freescale.com>
| * | arm/ls102xa: use a array to define pexmscportsrMinghuan Lian2015-02-24-2/+1
| | | | | | | | | | | | | | | Signed-off-by: Minghuan Lian <Minghuan.Lian@freescale.com> Reviewed-by: York Sun <yorksun@freescale.com>
| * | arm/ls102xa: create TLB to map PCIe regionMinghuan Lian2015-02-24-10/+207
| | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | LS1021A's PCIe1 region begins 0x40_00000000; PCIe2 begins 0x48_00000000. In order to access PCIe device, we must create TLB to map the 40bit physical address to 32bit virtual address. This patch will enable MMU after DDR is available and creates MMU table in DRAM to map all 4G space; then, re-use the reserved space to map PCIe region. The following the mapping layout. VA mapping: ------- <---- 0GB | | | | |-------| <---- 0x24000000 |///////| ===> 192MB VA map for PCIe1 with offset 0x40_0000_0000 |-------| <---- 0x300000000 | | |-------| <---- 0x34000000 |///////| ===> 192MB VA map for PCIe2 with offset 0x48_0000_0000 |-------| <---- 0x40000000 | | |-------| <---- 0x80000000 DDR0 space start |\\\\\\\| |\\\\\\\| ===> 2GB VA map for 2GB DDR0 Memory space |\\\\\\\| ------- <---- 4GB DDR0 space end Signed-off-by: Minghuan Lian <Minghuan.Lian@freescale.com> Reviewed-by: York Sun <yorksun@freescale.com>
| * | arm: ls102xa: Define default values for some CCSR macrosAlison Wang2015-02-24-0/+37
| | | | | | | | | | | | | | | | | | | | | | | | This patch is to define default values for some CCSR macros to make header files cleaner. Signed-off-by: Alison Wang <alison.wang@freescale.com> Reviewed-by: York Sun <yorksun@freescale.com>
| * | drivers/mc: Migrated MC Flibs to 0.5.2J. German Rivera2015-02-24-52/+592
| | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | Upgrade Manage Complex (MC) flib API to 0.5.2. Rename directory fsl_mc to fsl-mc. Change the fsl-mc node in Linux device tree from "fsl,dprcr" to "fsl-mc". Print MC version info when appropriate. Signed-off-by: J. German Rivera <German.Rivera@freescale.com> Signed-off-by: Lijun Pan <Lijun.Pan@freescale.com> Reviewed-by: York Sun <yorksun@freescale.com>
| * | armv8/ls2085a_emu: Enable sync of refreshYork Sun2015-02-24-0/+1
| | | | | | | | | | | | | | | | | | | | | Enable sync of DDR refresh for LS2085a platform. GPP DDR controllers stay in sync. DP-DDR has only one controller so it does no harm. Signed-off-by: York Sun <yorksun@freescale.com>
| * | armv8/fsl-lsch3: Enable erratum workround for A008514York Sun2015-02-24-0/+1
| | | | | | | | | | | | | | | | | | Erratum A008514 appleis to ls2085a. Signed-off-by: York Sun <yorksun@freescale.com>
| * | armv8/fsl-lsch3: Enable workaround for A008336York Sun2015-02-24-0/+4
| | | | | | | | | | | | | | | | | | Erratum A008336 applied to LS2085A. Signed-off-by: York Sun <yorksun@freescale.com>
| * | ls2085/configs: Ensure right banners are printed for EMU and SIMUBhupesh Sharma2015-02-24-3/+6
| | | | | | | | | | | | | | | | | | | | | | | | This patch enusres that right banners are printed for LS2085A emulator and simulator platforms. Signed-off-by: Bhupesh Sharma <bhupesh.sharma@freescale.com> Reviewed-by: York Sun <yorksun@freescale.com>
| * | ARMv8/ls2085a: Move kernel image load addressStuart Yoder2015-02-24-1/+1
| | | | | | | | | | | | | | | | | | | | | | | | Move the load address of the kernel image to get it away from the region of the uncompressed kernel. Signed-off-by: Stuart Yoder <stuart.yoder@freescale.com> Reviewed-by: York Sun <yorksun@freescale.com>
| * | ARMv8/ls2085a: Switch to passing earlycon to kernelArnab Basu2015-02-24-4/+4
| | | | | | | | | | | | | | | | | | | | | | | | Since Linux v3.16-rc1 earlyprintk has been removed for arm64. Switch to using earlycon. Signed-off-by: Arnab Basu <arnab.basu@freescale.com> Signed-off-by: York Sun <yorksun@freescale.com>
| * | driver/ddr/fsl: Add sync of refreshYork Sun2015-02-24-0/+64
| | | | | | | | | | | | | | | | | | | | | Add sync of refresh for multiple DDR controllers. DDRC initialization needs to complete first. Code is re-ordered to keep refresh close. Signed-off-by: York Sun <yorksun@freescale.com>
| * | ARMv8/LS2085A: Adjust system clock and DDR clockYork Sun2015-02-24-1/+2
| | | | | | | | | | | | | | | | | | Set system clock to 100MHz and DDR clock to 133MHz. Signed-off-by: York Sun <yorksun@freescale.com>
| * | ARMv8/LS2085A: HugeTLB support is required by default in LS NADKKuldip Giroh2015-02-24-1/+3
| | | | | | | | | | | | | | | | | | | | | | | | | | | | | | LS NADK memory manager by default works on HugeTLB. Hence bootargs must include parameters default_hugepagesz (default hugepagesize, hugepagesz (hugepage size) and hugepages (number of hugepages to be reserved in kernel for the given size). Signed-off-by: Kuldip Giroh <kuldip.giroh@freescale.com> Reviewed-by: York Sun <yorksun@freescale.com>
| * | driver/ddr/fsl: Fix a typo in timing_cfg_8 calculationYork Sun2015-02-24-1/+1
| | | | | | | | | | | | | | | | | | wwt_bg should match rrt_bg. It was a typo in driver. Signed-off-by: York Sun <yorksun@freescale.com>
| * | ARMv8/LS2085A: Enable auto precharge for DP-DDRYork Sun2015-02-24-0/+1
| | | | | | | | | | | | | | | | | | | | | DP-DDR benefits from auto precharge because of its specific application. Signed-off-by: York Sun <yorksun@freescale.com>
| * | driver/ddr/fsl: Add support for multiple DDR clocksYork Sun2015-02-24-159/+190
| | | | | | | | | | | | | | | | | | | | | | | | | | | Controller number is passed for function calls to support individual DDR clock, depending on SoC implementation. It is backward compatible with exising platforms. Multiple clocks have been verifyed on LS2085A emulator. Signed-off-by: York Sun <yorksun@freescale.com>
| * | armv8/fsl-lsch3: Add support for second DDR clockYork Sun2015-02-24-2/+21
| | | | | | | | | | | | | | | | | | | | | | | | FSL-LSCH3 platforms can have multiple DDR clocks. LS2085A has one clock for general DDR controlers, and another clock for DP-DDR. DDR driver needs to change to support multiple clocks. Signed-off-by: York Sun <yorksun@freescale.com>
| * | driver/ddr/fsl: Add workround for erratumn A008514York Sun2015-02-24-5/+17
| | | | | | | | | | | | | | | | | | | | | Erratum A008514 workround requires writing register eddrtqcr1 with value 0x63b20002. Signed-off-by: York Sun <yorksun@freescale.com>
| * | driver/ddr/fsl: Add workaround for A008336York Sun2015-02-24-0/+27
| | | | | | | | | | | | | | | | | | | | | Erratum A008336 requires setting EDDRTQCR1[2] in DDRC DCSR space for 64-bit DDR controllers. Signed-off-by: York Sun <yorksun@freescale.com>
| * | driver/ddr/fsl: Adjust CAS to preamble override for emulatorYork Sun2015-02-24-1/+5
| | | | | | | | | | | | | | | | | | | | | | | | | | | On ZeBu emulator, CAS to preamble overrides need to be set to satisfy the timing. This only impact platforms with CONFIG_EMU. These should be set before MEM_EN is set. Signed-off-by: York Sun <yorksun@freescale.com>
generated by cgit v1.1 at 2024-10-31 15:25:55 +0000