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| author | York Sun <yorksun@freescale.com> | 2015-01-06 13:19:01 -0800 |
|---|---|---|
| committer | York Sun <yorksun@freescale.com> | 2015-02-24 13:10:16 -0800 |
| commit | 4f2532c4a4a34f0241ef9bc921044772f19f928d (patch) | |
| tree | 29eca9e67cf592301bba0785418178816f7a82b9 | |
| parent | 1478fdef526f7881f809f6dcce1d63fc6cd080d6 (diff) | |
| download | u-boot-imx-4f2532c4a4a34f0241ef9bc921044772f19f928d.zip u-boot-imx-4f2532c4a4a34f0241ef9bc921044772f19f928d.tar.gz u-boot-imx-4f2532c4a4a34f0241ef9bc921044772f19f928d.tar.bz2 | |
armv8/ls2085a_emu: Enable sync of refresh
Enable sync of DDR refresh for LS2085a platform. GPP DDR controllers
stay in sync. DP-DDR has only one controller so it does no harm.
Signed-off-by: York Sun <yorksun@freescale.com>
| -rw-r--r-- | include/configs/ls2085a_emu.h | 1 |
1 files changed, 1 insertions, 0 deletions
diff --git a/include/configs/ls2085a_emu.h b/include/configs/ls2085a_emu.h index 2d2e1ea..a02d694 100644 --- a/include/configs/ls2085a_emu.h +++ b/include/configs/ls2085a_emu.h @@ -20,4 +20,5 @@ #define SPD_EEPROM_ADDRESS SPD_EEPROM_ADDRESS1 #define CONFIG_SYS_SPD_BUS_NUM 1 /* SPD on I2C bus 1 */ +#define CONFIG_FSL_DDR_SYNC_REFRESH #endif /* __LS2_EMU_H */ |