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* keystone2: k2g: add env script to load firmware initramfs as part of boot flowMurali Karicheri2016-10-01-1/+5
| | | | | | | | | | | | | | | On K2G, the PCIe SerDes h/w is a re-use from other K2 devices and SerDes driver requires a firmware image to initialize the SerDes h/w device. This is firmware is part of the initramfs file that is loaded to memory in u-boot and passed to kernel as in other K2 platforms. This patch customize the u-boot env to have this done automatically when the K2G EVM boots up. With this, a user may be able to boot the EVM with a standard PCIe card at the x1 PCIe slot and release image and test PCIe devices such as NIC, SATA etc. Signed-off-by: Murali Karicheri <m-karicheri2@ti.com> Signed-off-by: Lokesh Vutla <lokeshvutla@ti.com> Reviewed-by: Tom Rini <trini@konsulko.com>
* board: k2g: Enable ECC byte laneLokesh Vutla2016-10-01-2/+1
| | | | | | | Enable ECC byte lane for k2g-evm Signed-off-by: Lokesh Vutla <lokeshvutla@ti.com> Reviewed-by: Tom Rini <trini@konsulko.com>
* board: ks2: Enable ECC using detected DDR sizeLokesh Vutla2016-10-01-0/+3
| | | | | | | | | EEC is being enabled based on the ddr size populated by SPD data. But not all keystone platforms have SPD data to detect ddr3 size. So, enable ECC using the detected DDR size. Signed-off-by: Lokesh Vutla <lokeshvutla@ti.com> Reviewed-by: Tom Rini <trini@konsulko.com>
* fastboot: move FASTBOOT_FLASH options into KconfigPetr Kulhavy2016-10-01-5/+32
| | | | | | | | | | | | | Move FASTBOOT_MBR_NAME and FASTBOOT_GPT_NAME into Kconfig. Add dependency on the FASTBOOT_FLASH setting (also for FASTBOOT_MBR_NAME). Remove the now redundant GPT_ENTRY_NAME. Signed-off-by: Petr Kulhavy <brain@jikos.cz> Reviewed-by: Tom Rini <trini@konsulko.com> Acked-by: Steve Rae <steve.rae@raedomain.com> Reviewed-by: Simon Glass <sjg@chromium.org> [trini: Add FIXME about xxx_PARTITION needing to be in Kconfig] Signed-off-by: Tom Rini <trini@konsulko.com>
* disk: part: refactor generic name creation for DOS and ISOPetr Kulhavy2016-10-01-53/+50
| | | | | | | | | | | | | In both DOS and ISO partition tables the same code to create partition name like "hda1" was repeated. Code moved to into a new function part_set_generic_name() in part.c and optimized. Added recognition of MMC and SD types, name is like "mmcsda1". Signed-off-by: Petr Kulhavy <brain@jikos.cz> Reviewed-by: Tom Rini <trini@konsulko.com> Acked-by: Steve Rae <steve.rae@raedomain.com> Reviewed-by: Simon Glass <sjg@chromium.org>
* fastboot: add support for writing MBRPetr Kulhavy2016-10-01-6/+121
| | | | | | | | | | | | Add special target "mbr" (otherwise configurable via CONFIG_FASTBOOT_MBR_NAME) to write MBR partition table. Partitions are now searched using the generic function which finds any partiiton by name. For MBR the partition names hda1, sda1, etc. are used. Signed-off-by: Petr Kulhavy <brain@jikos.cz> Reviewed-by: Tom Rini <trini@konsulko.com> Acked-by: Steve Rae <steve.rae@raedomain.com> Reviewed-by: Simon Glass <sjg@chromium.org>
* disk: part: implement generic function part_get_info_by_name()Petr Kulhavy2016-10-01-33/+53
| | | | | | | | | | | | | | | | | So far partition search by name has been supported only on the EFI partition table. This patch extends the search to all partition tables. Rename part_get_info_efi_by_name() to part_get_info_by_name(), move it from part_efi.c into part.c and make it a generic function which traverses all part drivers and searches all partitions (in the order given by the linked list). For this a new variable struct part_driver.max_entries is added, which limits the number of partitions searched. For EFI this was GPT_ENTRY_NUMBERS. Similarly the limit is defined for DOS, ISO, MAC and AMIGA partition tables. Signed-off-by: Petr Kulhavy <brain@jikos.cz> Reviewed-by: Tom Rini <trini@konsulko.com> Acked-by: Steve Rae <steve.rae@raedomain.com>
* bootm: fix passing argc to standalone appsZubair Lutfullah Kakakhel2016-10-01-3/+1
| | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | This bug appears in b6396403 which makes u-boot unable to pass arguments via bootm to a standalone application without this patch. Steps to reproduce. Compile a u-boot. Use mkimage to package the standalone hello_world.bin file. e.g. For the MIPS Boston platform mkimage -n "hello" -A mips -O u-boot -C none -T standalone \ -a 0xffffffff80200000 -d hello_world.bin \ -ep 0xffffffff80200000 hello_out Then tftp hello_out and run it using boston # dhcp 192.168.154.45:hello_out ... boston # bootm $loadaddr 123 321 Without the patch the following output is observed. boston # bootm $loadaddr 123 321 Image Name: hello Image Type: MIPS U-Boot Standalone Program (uncompressed) Data Size: 1240 Bytes = 1.2 KiB Load Address: 80200000 Entry Point: 80200000 Verifying Checksum ... OK Loading Standalone Program ... OK Example expects ABI version 8 Actual U-Boot ABI version 8 Hello World argc = 0 argv[0] = "0xffffffff88000000" With the patch, you see the following. boston # bootm $loadaddr 123 321 Image Name: hello Image Type: MIPS U-Boot Standalone Program (uncompressed) Data Size: 1240 Bytes = 1.2 KiB Load Address: 80200000 Entry Point: 80200000 Verifying Checksum ... OK Loading Standalone Program ... OK Example expects ABI version 8 Actual U-Boot ABI version 8 Hello World argc = 3 argv[0] = "0xffffffff88000000" argv[1] = "123" argv[2] = "321" argv[3] = "<NULL>" Without the patch, the go command at the entry point seems to work. boston # go 0xffffffff80200000 123 321 Example expects ABI version 8 Actual U-Boot ABI version 8 Hello World argc = 3 argv[0] = "0xffffffff80200000" argv[1] = "123" argv[2] = "321" argv[3] = "<NULL>" Hit any key to exit ... Signed-off-by: Zubair Lutfullah Kakakhel <Zubair.Kakakhel@imgtec.com> Reviewed-by: Simon Glass <sjg@chromium.org>
* input: specify the default of I8042_KEYB in more correct mannerMasahiro Yamada2016-10-01-3/+1
| | | | | | | | | | Creating multiple entries of "config FOO" often gives us bad experiences. In this case, we should specify "default X86" as platforms that want this keyboard by default. Signed-off-by: Masahiro Yamada <yamada.masahiro@socionext.com> Acked-by: Marek Vasut <marex@denx.de> Reviewed-by: Simon Glass <sjg@chromium.org>
* sandbox, x86: select DM_KEYBOARD instead of default y entryMasahiro Yamada2016-10-01-6/+2
| | | | | | | | | | Once we migrate to DM-based drivers, we cannot go back to legacy ones, i.e. config options like DM_* are not user-configurable. Make SANDBOX and X86 select DM_KEYBOARD like other platforms do. Signed-off-by: Masahiro Yamada <yamada.masahiro@socionext.com> Reviewed-by: Simon Glass <sjg@chromium.org>
* Merge branch 'master' of git://git.denx.de/u-boot-nds32Tom Rini2016-09-30-74/+77
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| * nds32: Support relocation.rick2016-09-29-74/+77
| | | | | | | | | | | | | | Enable pie option for relocation. Signed-off-by: rick <rick@andestech.com> Cc: Andes <uboot@andestech.com>
* | Merge branch 'master' of git://git.denx.de/u-boot-usbTom Rini2016-09-30-156/+574
|\ \ | | | | | | | | | | | | | | | | | | Signed-off-by: Tom Rini <trini@konsulko.com> Conflicts: include/configs/dra7xx_evm.h
| * | drivers: usb: xhci-fsl: Implement Erratum A-010151 for FSL USB3 controllerSriram Dash2016-09-27-0/+41
| | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | Currently the controller by default enables the Receive Detect feature in P3 mode in USB 3.0 PHY. However, USB 3.0 PHY does not reliably support receive detection in P3 mode. Enabling the USB3 controller to configure USB in P2 mode whenever the Receive Detect feature is required. Signed-off-by: Sriram Dash <sriram.dash@nxp.com> Signed-off-by: Rajesh Bhagat <rajesh.bhagat@nxp.com>
| * | usb: fsl: Renaming fdt_fixup_erratum and fdt_fixup_usb_erratumSriram Dash2016-09-27-22/+23
| | | | | | | | | | | | | | | | | | | | | | | | The functions fdt_fixup_erratum and fdt_fixup_usb_erratum are fsl/nxp specific. So, make them explicit by renaming them fsl_fdt_fixup_erratum and fsl_fdt_fixup_usb_erratum Signed-off-by: Sriram Dash <sriram.dash@nxp.com>
| * | usb: fsl: Rename fdt_fixup_dr_usbSriram Dash2016-09-27-36/+36
| | | | | | | | | | | | | | | | | | | | | | | | The function fdt_fixup_dr_usb is specific to fsl/nxp. So, make the function name explicit and rename fdt_fixup_dr_usb into fsl_fdt_fixup_dr_usb. Signed-off-by: Sriram Dash <sriram.dash@nxp.com>
| * | apalis_t30: colibri_imx7: colibri_t30: fix ethernet functionalityMarcel Ziswiler2016-09-27-5/+4
| | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | Since commit aa7a648747d8c704a9a81c9e493d386930724e9d ("net: Stop including NFS overhead in defragment max") the following has been reproducibly observed while trying to transfer data over TFTP: Load address: 0x80408000 Loading: EHCI timed out on TD - token=0x8008d80 T EHCI timed out on TD - token=0x88008d80 Rx: failed to receive: -5 This patch fixes this by lowering our TFTP block size to be within the standard maximal de-fragmentation aka IP packet size again. Signed-off-by: Marcel Ziswiler <marcel.ziswiler@toradex.com>
| * | configs: colibri_vf_defconfig: Enable USB driver model for Colibri VybridSanchayan Maity2016-09-27-0/+1
| | | | | | | | | | | | | | | | | | Enable USB driver model for Toradex Colibri Vybrid modules. Signed-off-by: Sanchayan Maity <maitysanchayan@gmail.com>
| * | ARM: dts: vf-colibri: Enable USB device tree node for Colibri VybridSanchayan Maity2016-09-27-0/+11
| | | | | | | | | | | | | | | | | | Enable USB device tree node for Toradex Colibri Vybrid module. Signed-off-by: Sanchayan Maity <maitysanchayan@gmail.com>
| * | ARM: dts: vf: Add device tree node for USB on VybridSanchayan Maity2016-09-27-0/+14
| | | | | | | | | | | | | | | | | | Add device tree node for USB peripheral on Vybrid. Signed-off-by: Sanchayan Maity <maitysanchayan@gmail.com>
| * | usb: host: ehci-vf: Migrate Vybrid USB to driver modelSanchayan Maity2016-09-27-7/+201
| | | | | | | | | | | | | | | | | | Add driver model support for Vybrid USB driver. Signed-off-by: Sanchayan Maity <maitysanchayan@gmail.com>
| * | cmd: dfu: Add error handling for failed registrationSanchayan Maity2016-09-27-1/+6
| | | | | | | | | | | | | | | | | | | | | | | | | | | Without this, if g_dnl_register() fails, DFU code continues on blindly and crashes. This fix makes it simply print an error message instead. Signed-off-by: Sanchayan Maity <maitysanchayan@gmail.com> [l.majewski@samsung.com - some manual tweaks needed]
| * | dra7x: configs: enable SPL-DFU supportB, Ravi2016-09-27-3/+19
| | | | | | | | | | | | | | | | | | | | | | | | This patch enables the SPL-DFU support for dra7x platform. Signed-off-by: Ravi Babu <ravibabu@ti.com> Reviewed-by: Tom Rini <trini@konsulko.com>
| * | dra7x: boot: add dfu bootmode supportB, Ravi2016-09-27-2/+15
| | | | | | | | | | | | | | | | | | | | | | | | This patch enables the DFU boot mode support for dra7x platform. Signed-off-by: Ravi Babu <ravibabu@ti.com> Reviewed-by: Tom Rini <trini@konsulko.com>
| * | spl: dfu: adding dfu support functions for SPL-DFUB, Ravi2016-09-27-0/+66
| | | | | | | | | | | | | | | | | | | | | Adding support functions to run dfu spl commands. Signed-off-by: Ravi Babu <ravibabu@ti.com> Reviewed-by: Tom Rini <trini@konsulko.com>
| * | common: dfu: saperate the dfu common functionalityB, Ravi2016-09-27-59/+92
| | | | | | | | | | | | | | | | | | | | | | | | | | | The cmd_dfu functionality is been used by both SPL and u-boot, saperating the core dfu functionality moving it to common/dfu.c. Signed-off-by: Ravi Babu <ravibabu@ti.com> Reviewed-by: Tom Rini <trini@konsulko.com>
| * | spl: dfu: add dfu support in SPLB, Ravi2016-09-27-0/+32
| | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | Traditionally the DFU support is available only as part 2nd stage boot loader(u-boot) and DFU is not supported in SPL. The SPL-DFU feature is useful for boards which does not have MMC/SD, ethernet boot mechanism to boot the board and only has USB inteface. This patch add DFU support in SPL with RAM memory device support to load and execute u-boot. And then leverage full functionality DFU in u-boot to flash boot inital binary images to factory or bare-metal boards to memory devices like SPI, eMMC, MMC/SD card using USB interface. This SPL-DFU support can be enabled through Menuconfig->Boot Images->Enable SPL-DFU support Signed-off-by: Ravi Babu <ravibabu@ti.com> Reviewed-by: Tom Rini <trini@konsulko.com>
| * | drivers: usb: xhci-fsl: Change burst beat and outstanding pipelined ↵Sriram Dash2016-09-27-0/+13
| | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | transfers requests This is required for better performance, and performs below tuning: 1. Enable burst length set, and define it as 4/8/16. 2. Set burst request limit to 16 requests. Signed-off-by: Rajesh Bhagat <rajesh.bhagat@nxp.com> Signed-off-by: Sriram Dash <sriram.dash@nxp.com>
| * | colibri_t30: fix usb ethernet functionalityMarcel Ziswiler2016-09-27-0/+1
| | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | Since commit aa7a648747d8c704a9a81c9e493d386930724e9d ("net: Stop including NFS overhead in defragment max") the following has been reproducibly observed while trying to transfer data over TFTP: Load address: 0x80408000 Loading: EHCI timed out on TD - token=0x8008d80 T EHCI timed out on TD - token=0x88008d80 Rx: failed to receive: -5 This patch fixes this by upping our maximal de-fragmentation aka IP packet size again. Signed-off-by: Marcel Ziswiler <marcel.ziswiler@toradex.com>
| * | net: asix: Fix ASIX 88772B with driver modelAlban Bedel2016-09-27-24/+3
| | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | Commit 147271209a9d ("net: asix: fix operation without eeprom") added a special handling for ASIX 88772B that enable another type of header. This break the driver in DM mode as the extra handling needed in the receive path is missing. However this new header mode is not required and only seems to increase the code complexity, so this patch revert this part of commit 147271209a9d. This also reverts commit 41d1258aceb45b45f9e68f67a9c40f0afbc09dc9 ("net: asix: Fix AX88772B when used with DriverModel") of late. Fixes: 147271209a9d ("net: asix: fix operation without eeprom") Signed-off-by: Alban Bedel <alban.bedel@avionic-design.de> Signed-off-by: Marcel Ziswiler <marcel.ziswiler@toradex.com>
* | | mpc85xx: powerpc: usb: Update the list of Socs afftected by erratum A006261Sriram Dash2016-09-28-12/+5
| | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | Apply the erratum A006261 for the following Socs: P2041 rev 2.0, P2040 rev 2.0, P5040 rev 2.0, 2.1 Do not apply erratum A006261 for the following Socs: T4160, T4080, T1040, T1042, T1020, T1022, T2080, T2081 Erratum A006261 is applicable for the following Socs: P1010(1.0, 2.0), P2041(1.0, 1.1, 2.0, 2.1), P2040(1.0, 1.1, 2.0, 2.1), P3041(1.0, 1.1, 2.0, 2.1), P5010(1.0, 2.0), P5020(1.0, 2.0), P5021(1.0, 2.0), T4240(1.0, 2.0), P5040(1.0,2.0,2.1). Signed-off-by: Sriram Dash <sriram.dash@nxp.com> Signed-off-by: Rajesh Bhagat <rajesh.bhagat@nxp.com> Reviewed-by: York Sun <york.sun@nxp.com>
* | | mpc85xx: powerpc: usb: Enable Usb phy initialisation settings for P1010Sriram Dash2016-09-28-0/+3
| | | | | | | | | | | | | | | | | | | | | | | | | | | CONFIG_SYS_FSL_USB1_PHY_ENABLE is set and the USB Phy offset are set to enable the initial setting of Usb Phy for P1010. Signed-off-by: Sriram Dash <sriram.dash@nxp.com> Signed-off-by: Rajesh Bhagat <rajesh.bhagat@nxp.com> Reviewed-by: York Sun <york.sun@nxp.com>
* | | mpc85xx: powerpc: usb: Modified the erratum A006261 according to endiannessSriram Dash2016-09-28-2/+2
| |/ |/| | | | | | | | | | | | | | | | | Modifies erratum implementation due to the fact that P3041, P5020, and P5040 are all big endian for the USB PHY registers, but they were specified little endian. Signed-off-by: Sriram Dash <sriram.dash@nxp.com> Signed-off-by: Rajesh Bhagat <rajesh.bhagat@nxp.com> Reviewed-by: York Sun <york.sun@nxp.com>
* | Merge git://www.denx.de/git/u-boot-ppc4xxTom Rini2016-09-27-7/+0
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| * | CPCI4052: Remove CONFIG_AUTO_COMPLETE and custom baud rate tableTom Rini2016-09-27-7/+0
| |/ | | | | | | | | | | | | | | | | | | This board is getting close to or exceeding the size limit again, remove CONFIG_AUTO_COMPLETE to save space and while in here switch to the default and slightly less complete default baudrate table. Cc: Matthias Fuchs <matthias.fuchs@esd-electronics.com> Signed-off-by: Tom Rini <trini@konsulko.com> Signed-off-by: Stefan Roese <sr@denx.de>
* | Merge branch 'master' of git://git.denx.de/u-boot-tegraTom Rini2016-09-27-1235/+3555
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| * | ARM: tegra: flush caches via SMC callStephen Warren2016-09-27-0/+24
| | | | | | | | | | | | | | | | | | | | | | | | | | | | | | On Tegra186, it is necessary to perform an SMC to fully flush all caches; flushing/cleaning by set/way is not enough. Implement the required hook to make this happen. Signed-off-by: Stephen Warren <swarren@nvidia.com> Reviewed-by: Simon Glass <sjg@chromium.org> Signed-off-by: Tom Warren <twarren@nvidia.com>
| * | ARM: tegra: fix ULPI PHY on Ventana and SeaboardStephen Warren2016-09-27-2/+12
| | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | Commit ce02a71c2374 "tegra: dts: Sync tegra20 device tree files with Linux" enabled the ULPI USB port on Ventana, but made no attempt to ensure that U-Boot code could handle this. In practice, various code is missing, and various configuration options are not enabled, which causes U-Boot to hang when attempting to initialize this USB port. This patch enables ULPI PHY support on Ventana, and adds the required pinmux setup for the port to operate. Note that Ventana is so similar to Seaboard that this change is made in the Seaboard board file, which is shared with Ventana. Seaboard also has the ULPI USB port wired up in hardware, although to an internal port that often doesn't have anything attached to it. However, the DT nodes for the USB controller and PHY had different status property values, so the port was not initialized by U-Boot. Fix this inconsistency, and enable the ULPI port, just like in the Linux kernel DT. This likewise requires enabling ULPI support in the Seaboard defconfig. Cc: Marcel Ziswiler <marcel.ziswiler@toradex.com> Signed-off-by: Stephen Warren <swarren@nvidia.com> Reviewed-by: Simon Glass <sjg@chromium.org> Signed-off-by: Tom Warren <twarren@nvidia.com>
| * | ARM: tegra: fix USB controller aliasesStephen Warren2016-09-27-6/+9
| | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | Some boards have a different set of USB controllers enabled in DT than the set referenced by /alias entries. This patch fixes that. For example, this avoids the following message while booting on Ventana, which is caused by the fact that the USB0 controller had no alias, and defaulted to wanting a sequence number of 0, which was later explicitly requested by the alias for USB controller 2. USB2: Device 'usb@c5008000': seq 0 is in use by 'usb@c5000000' This didn't affect USB operation in any way though. Related, there's no need for the USB controller aliases to have an order that's different from the HW order, so re-order any aliases to match the HW ordering. This has the benefit that since USB controller 0 is the only one that supports device-mode in HW, and U-Boot only supports enabling device move on controller 0, there's now good synergy in the ordering! For Tegra20, that's not relevant at present since USB device mode doesn't work correctly on that SoC, but it will save some head-scratching later. This patch doesn't fix the colibri_t20 board, even though it has the same issue, since Marcel already sent a patch for that. Cc: Marcel Ziswiler <marcel.ziswiler@toradex.com> Signed-off-by: Stephen Warren <swarren@nvidia.com> Reviewed-by: Simon Glass <sjg@chromium.org> Signed-off-by: Tom Warren <twarren@nvidia.com> Tested-by: Marcel Ziswiler <marcel.ziswiler@toradex.com> Tested-on: Harmony and Ventana
| * | ARM: tegra: fix USB ULPI PHY reset signal inversion confusionStephen Warren2016-09-27-4/+15
| | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | USB ULPI PHY reset signals are typically active low. Consequently, they should be marked as GPIO_ACTIVE_LOW in device tree, and indeed they are in the Linux kernel DTs, and in DT properties that U-Boot doesn't yet use. However, in DT properties that U-Boot does use, the value has been set to 0 (== GPIO_ACTIVE_HIGH) to work around a bug in U-Boot. This change fixes the DT to correctly represent the HW, and fixes the Tegra USB driver to cope with the fact that dm_gpio_set_value() internally handles any inversions implied by the DT value GPIO_ACTIVE_LOW. Cc: Marcel Ziswiler <marcel.ziswiler@toradex.com> Signed-off-by: Stephen Warren <swarren@nvidia.com> Reviewed-by: Simon Glass <sjg@chromium.org> Signed-off-by: Tom Warren <twarren@nvidia.com>
| * | i2c: tegra: only use new clock/reset APIsStephen Warren2016-09-27-57/+11
| | | | | | | | | | | | | | | | | | | | | | | | | | | | | | Now that the standard clock/reset APIs are available for all Tegra SoCs, convert the I2C driver to use them exclusively, and remove any references to the custom Tegra-specific APIs. Cc: Heiko Schocher <hs@denx.de> Signed-off-by: Stephen Warren <swarren@nvidia.com> Signed-off-by: Tom Warren <twarren@nvidia.com>
| * | mmc: tegra: only use new clock/reset APIsStephen Warren2016-09-27-40/+5
| | | | | | | | | | | | | | | | | | | | | | | | | | | | | | Now that the standard clock/reset APIs are available for all Tegra SoCs, convert the MMC driver to use them exclusively, and remove any references to the custom Tegra-specific APIs. Cc: Jaehoon Chung <jh80.chung@samsung.com> Signed-off-by: Stephen Warren <swarren@nvidia.com> Signed-off-by: Tom Warren <twarren@nvidia.com>
| * | ARM: tegra: enable standard clock/reset APIs everywhereStephen Warren2016-09-27-3/+11
| | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | Implementations of the standard clock and reset APIs are available on all Tegra SoCs now, so enable compilation of those uclasses. Enable the Tegra CAR drivers for all SoCs prior to the BPMP being available. This provides an implementation of those APIs everywhere. Signed-off-by: Stephen Warren <swarren@nvidia.com> Signed-off-by: Tom Warren <twarren@nvidia.com>
| * | ARM: tegra: fix clock_get_periph_rate() for UART clocksStephen Warren2016-09-27-2/+36
| | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | Make clock_get_periph_rate() return the correct value for UART clocks. This change needs to be applied before the patches that enable CONFIG_CLK for Tegra SoCs before Tegra186, since enabling that option causes ns16550_serial_ofdata_to_platdata() to rely on clk_get_rate() for UART clocks, and clk_get_rate() eventually calls clock_get_periph_rate(). This change is a rather horrible hack, as explained in the comment added to the clock driver. I've tried fixing this correctly for all clocks as described in that comment, but there's too much fallout elsewhere. I believe the clock driver has a number of bugs which all cancel each-other out, and unravelling that chain is too complex at present. This change is the smallest change that fixes clock_get_periph_rate() for UART clocks while guaranteeing no change in behaviour for any other clock, which avoids other regressions. Signed-off-by: Stephen Warren <swarren@nvidia.com> Reviewed-by: Simon Glass <sjg@chromium.org> Signed-off-by: Tom Warren <twarren@nvidia.com>
| * | clock: implement a driver for the Tegra CARStephen Warren2016-09-27-0/+111
| | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | Implement a clock uclass driver for the Tegra CAR. This allows clients to use standard clock APIs on Tegra. This device is intended to be instantiated by the core Tegra CAR driver, rather than being instantiated directly from DT. The implementation uses the existing custom Tegra- specific clock APIs to avoid coupling the series with significant refactoring of the existing Tegra clock/clock code. The driver currently only supports peripheral clocks, and avoids support for other clocks such as PLLs and external clocks. This should be sufficient to convert over all Tegra peripheral drivers, and avoids a complex implementation which calls different Tegra-specific clock APIs based on the type of clock being manipulated. Signed-off-by: Stephen Warren <swarren@nvidia.com> Signed-off-by: Tom Warren <twarren@nvidia.com>
| * | reset: implement a driver for the Tegra CARStephen Warren2016-09-27-0/+80
| | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | Implement a reset uclass driver for the Tegra CAR. This allows clients to use standard reset APIs on Tegra. This device is intended to be instantiated by the core Tegra CAR driver, rather than being instantiated directly from DT. The implementation uses the existing custom Tegra- specific reset APIs to avoid coupling the series with significant refactoring of the existing Tegra clock/reset code. Signed-off-by: Stephen Warren <swarren@nvidia.com> Signed-off-by: Tom Warren <twarren@nvidia.com>
| * | misc: implement Tegra CAR core driverStephen Warren2016-09-27-0/+76
| | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | The Tegra CAR (Clock And Reset) module provides control of most clocks and reset signals within the Tegra SoC. This change implements a driver for this module. However, since the module implements multiple kinds of services (clocks, resets, perhaps more), all this driver does is bind various sub-devices, which in turn provide the real services. This driver is essentially an "MFD" (Multi-Function Device) in Linux kernel speak. Signed-off-by: Stephen Warren <swarren@nvidia.com> Signed-off-by: Tom Warren <twarren@nvidia.com>
| * | ARM: tegra: add APIs the clock uclass driver will needStephen Warren2016-09-27-86/+323
| | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | A future patch will implement a clock uclass driver for Tegra. That driver will call into Tegra's existing clock code to simplify the transition; this avoids tieing the clock uclass patches into significant refactoring of the existing custom clock API implementation. Some of the Tegra clock APIs that manipulate peripheral clocks require both the peripheral clock ID and parent clock ID to be passed in together. However, the clock uclass API does not require any such "parent" parameter, so the clock driver must determine this information itself. This patch implements new Tegra- specific clock API clock_get_periph_parent() for this purpose. The new API is implemented in the core Tegra clock code rather than SoC- specific clock code. The implementation uses various SoC-/clock-specific data. That data is only available in SoC-specific clock code. Consequently, two new internal APIs are added that enable the core clock code to retrieve this information from the SoC-specific clock code. Due to the structure of the Tegra clock code, this leads to some unfortunate code duplication. However, this situation predates this patch. Ideally, future work will de-duplicate the Tegra clock code, and migrate it into drivers/clk/tegra. However, such refactoring is kept separate from this series. Signed-off-by: Stephen Warren <swarren@nvidia.com> Signed-off-by: Tom Warren <twarren@nvidia.com>
| * | ARM: tegra: add peripheral clock init tableStephen Warren2016-09-27-0/+134
| | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | Currently, Tegra peripheral drivers control two aspects of their HW module clock(s): 1) The clock enable/rate for the peripheral clock itself. 2) The system-level clock tree setup, i.e. the clock parent. Aspect 1 is reasonable, but aspect 2 is a system-level decision, not something that an individual peripheral driver should in general know about or influence. Such system-level knowledge ties the driver to a specific SoC implementation, even when they use generic APIs for clock manipulation, since they must have SoC-specific knowledge such as parent clock IDs. Limited exceptions exist, such as where peripheral HW is expected to dynamically switch between clock sources at run-time, such as CPU clock scaling or display clock conflict management in a multi-head scenario. This patch enhances the Tegra core code to perform system-level clock tree setup, in a similar fashion to the Linux kernel Tegra clock driver. This will allow future patches to simplify peripheral drivers by removing the clock parent setup logic. This change is required prior to converting peripheral drivers to use the standard clock APIs, since: 1) The clock uclass doesn't currently support a set_parent() operation. Adding one is possible, but not necessary at the moment. 2) The clock APIs retrieve all clock IDs from device tree, and the DT bindings for almost all peripherals only includes information about the relevant peripheral clocks, and not any potential parent clocks. Signed-off-by: Stephen Warren <swarren@nvidia.com> Signed-off-by: Tom Warren <twarren@nvidia.com>
| * | ARM: tegra: pull Tegra210 SoC DT from Linux v4.7Stephen Warren2016-09-27-252/+880
| | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | The primary benefit of this change is that it adds all missing clocks and resets properties to peripherals. This will allow peripheral drivers to migrate to the standard clock and reset APIs in the future. Main changes: * Brought in the correct Tegra210 CAR binding; the old file in U-Boot appears to be a renamed version of the Tegra124 bindings rather than the real Tegra210 version. * Conversion of SPI and UART nodes to standard DMA bindings. U-Boot doesn't use DMA so isn't affected. * Split of EHCI and USB PHY nodes. The EHCI nodes continue to contain all information required by U-Boot, so U-Boot is not affected. * Conversion of many magic numbers to named defines. * Addition of many nodes not used by U-Boot, including separation of the Tegra LIC (Legacy IRQ controller) and GIC. * Node sort order fixes. Remaining deltas relative to the Linux DT: * U-Boot has enabled PCIe for Tegra210, but the kernel hasn't yet. * The GPIO node compatible value in the kernel explicitly includes Tegra124 values whereas U-Boot does not. I'll send a kernel patch to correct this. Signed-off-by: Stephen Warren <swarren@nvidia.com> Signed-off-by: Tom Warren <twarren@nvidia.com>
generated by cgit v1.1 at 2024-11-09 22:55:04 +0000