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| author | Lokesh Vutla <lokeshvutla@ti.com> | 2016-08-27 17:19:16 +0530 |
|---|---|---|
| committer | Tom Rini <trini@konsulko.com> | 2016-10-01 20:05:07 -0400 |
| commit | e1ae357d4b6b46eae462dacf837bc6dbf997cf90 (patch) | |
| tree | 51aa28bf49e73b41e310a43b850d7b9599bfa60b | |
| parent | e92a6b2ee372d003602d71df427ec369be645cb6 (diff) | |
| download | u-boot-imx-e1ae357d4b6b46eae462dacf837bc6dbf997cf90.zip u-boot-imx-e1ae357d4b6b46eae462dacf837bc6dbf997cf90.tar.gz u-boot-imx-e1ae357d4b6b46eae462dacf837bc6dbf997cf90.tar.bz2 | |
board: k2g: Enable ECC byte lane
Enable ECC byte lane for k2g-evm
Signed-off-by: Lokesh Vutla <lokeshvutla@ti.com>
Reviewed-by: Tom Rini <trini@konsulko.com>
| -rw-r--r-- | arch/arm/mach-keystone/ddr3.c | 3 |
1 files changed, 1 insertions, 2 deletions
diff --git a/arch/arm/mach-keystone/ddr3.c b/arch/arm/mach-keystone/ddr3.c index 34606f4..6b92530 100644 --- a/arch/arm/mach-keystone/ddr3.c +++ b/arch/arm/mach-keystone/ddr3.c @@ -65,9 +65,8 @@ void ddr3_init_ddrphy(u32 base, struct ddr3_phy_config *phy_cfg) while ((__raw_readl(base + KS2_DDRPHY_PGSR0_OFFSET) & 0x1) != 0x1) ; - /* Disable ECC for K2G */ if (cpu_is_k2g()) { - clrbits_le32(base + KS2_DDRPHY_DATX8_4_OFFSET, 0x1); + setbits_le32(base + KS2_DDRPHY_DATX8_4_OFFSET, 0x1); clrbits_le32(base + KS2_DDRPHY_DATX8_5_OFFSET, 0x1); clrbits_le32(base + KS2_DDRPHY_DATX8_6_OFFSET, 0x1); clrbits_le32(base + KS2_DDRPHY_DATX8_7_OFFSET, 0x1); |